IRCC SMSC Corporation, IRCC Datasheet - Page 70

• Manufacturer Part Number: IRCC
• Description: INFRARED COMMUNICATIONS CONTROLLER
• Manufacturer: SMSC Corporation

Burst Mode Receive
DRQ Control
In DMA Burst Mode, DRQ remains active until
the entire DMA data block has been transferred,
as indicated by DMA Terminal Count (TC).
Since the FIFO Threshold is not used for DMA
transfer cycles, DRQ is asserted as soon as
FIFO Not Empty is true.
temporarily deactivate DRQ if the DMA block has
not been completely transferred but there is no
data left in the FIFO to transfer. As soon as
FIFO Not Empty becomes true, DRQ is
reasserted. The internal Refresh Interval signal
R e fr e s h In te r v a l
F IF O N O T E M PT Y
D M A E n a b le
R e fre sh In te rv a l
T x S e r v R e q
D M A B u r s t
F IF O F U L L
T x E n a b le
D M A E n ab le
D M A B u rst
R x E n ab le
FIGURE 39 - DMA BURST MODE TRANSMIT TIMING
D R Q
FIGURE 40 - DMA BURST MODE RECEIVE TIMING
T C
FIFO Not Empty can
D R Q
T C
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can also temporarily deactivate DRQ (see the 32
I/Ox Clock DMA Refresh Counter).
Example: Receive a 256-Byte IrDA Message
1.
2.
3.
4.
Setup and enable the DMA controller for the
256-byte message.
Enable the IrDA Receiver.
DRQ is asserted as soon as FIFO Not
Empty is true.
The DMA controller proceeds to empty the
FIFO until TC. DRQ is otherwise only de-
asserted when FIFO Not Empty is false or
Refresh Interval is active (Figure 40).