TS8388BMFSB_Q Atmel Corporation, TS8388BMFSB_Q Datasheet - Page 10

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TS8388BMFSB_Q

Manufacturer Part Number
TS8388BMFSB_Q
Description
ADC 8-bit 1 Gsps.
Manufacturer
Atmel Corporation
Datasheet
Timing Diagrams
Figure 2. TS8388B Timing Diagram (1 GSPS Clock Rate), Data Ready Reset, Clock Held at LOW Level
Figure 3. TS8388B Timing Diagram (1 GSPS Clock Rate), Data Ready Reset, Clock Held at HIGH Level
10
(CLK, CLKB)
(CLK, CLKB)
Data Ready
Data Ready
(VIN, VINB)
(VIN, VINB)
(DR, DRB)
OUTPUTS
(DR, DRB)
OUTPUTS
DIGITAL
DIGITAL
DRRB
DRRB
TS8388B
TDR = 1320 ps
X
X
N-1
N-1
1360 ps
1000 ps
1360 ps
1000 ps
TDR = 1320 ps
TRDR = 720 ps
TRDR = 720 ps
1 ns (min)
1 ns (min)
TA = 250 ps TBC
TA = 250 ps TBC
DATA
N-5
DATA
N-5
X
X
N
N
TDR = 1320 ps
TDR = 1320 ps
TC = 1000 ps
TC = 1000 ps
TC1
TC1
X
N+1
X
N+1
TPD: 4.0 Clock periods
TPD: 4.0 Clock periods
DATA
DATA
N-4
N-4
TC2
TC2
X
X
N+2
N+2
DATA
DATA
N-3
N-3
X
N+3
X
DATA
DATA
N-2
N-2
TOD = 1360 ps
TOD = 1360 ps
N+4
X
X
N+4
DATA
DATA
N-1
N-1
TD1 = TC1+TDR-TOD
TD1 = TC1+TDR-TOD
= TC1-40 ps = 460 ps
= TC1-40 ps = 460 ps
TD2 = TC2+TOD-TDR
= TC2+40 ps = 540 ps
TD2 = TC2+TOD-TDR
= TC2+40 ps = 540 ps
DATA
DATA
N
N
X
X
N+5
N+5
2144C–BDC–04/03
DATA
N+1
N+1

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