TS8388BMFSB_Q Atmel Corporation, TS8388BMFSB_Q Datasheet - Page 31

• Manufacturer Part Number: TS8388BMFSB_Q
• Description: ADC 8-bit 1 Gsps.
• Manufacturer: Atmel Corporation

Figure 31. Single-ended Clock Input (Ground common mode):
VCLK Common Mode = 0V; VCLKB = 0V; 4 dBm Typical Clock Input Power Level (into 50 termination resistor)
Differential ECL Clock
Input
Figure 32. Differential Clock Inputs (ECL Levels)
2144C–BDC–04/03
-0.8V
-1.8V
+0.5V
-0.5V
[mV]
[V]
VCLK
VCLK
No performance degradation (i.e.: due to timing jitter) is observed in this particular single-
ended configuration up to 1.2 GSPS Nyquist conditions (F
This is true so long as the inverted phase clock input pin is 50
of the neighboring shield ground pins, which constitutes the local Ground reference for the
inphase clock input.
Thus the TS8388B differential clock input buffer will fully reject the local ground noise (and any
capacitively and inductively coupled noise) as common mode effects. Moreover, a very low
phase noise sinewave generator must be used for enhanced jitter performance.
The typical inphase clock input amplitude is 1V peak to peak, centered on 0V (ground) com-
mon mode. This corresponds to a typical clock input power level of 4 dBm into the 50
termination resistor. Do not exceed 10 dBm to avoid saturation of the preamplifier input
transistors.
The inverted phase clock input is grounded through the 50
Note:
The clock inputs can be driven differentially with nominal -0.8V/-1.8V ECL levels.
In this mode, a low phase noise sinewave generator can be used to drive the clock inputs, fol-
lowed by a power splitter (hybrid junction) in order to obtain 180 degrees out of phase
sinewave signals. Biasing tees can be used for offseting the common mode voltage to ECL
levels.
Note: As the biasing tees propagation times are not matching, a tunable delay line is required
in order to ensure the signals to be 180 degrees out of phase especially at fast clock rates in
the GSPS range.
Do not exceed 10 dBm into the 50 termination resistor for single clock input power level.
VCLK
VCLKB
Common mode = -1.3V
VCLK = 0V
t
t
on package)
(external or
on package)
(external or
CLK or CLKB double pad (pins 37, 38 or 39, 40)
50Ω
CLK or CLKB double pad (pins 37, 38 or 39, 40)
CLK or CLKB
50Ω
CLK or CLKB
-2V
50Ω reverse termination
IN
50Ω reverse termination
= 600 MHz).
termination resistor.
terminated very closely to one
1 MΩ
1 MΩ
TS8388B
0.4 pF
0.4 pF
31