TS8388BMFSB_Q Atmel Corporation, TS8388BMFSB_Q Datasheet - Page 15

• Manufacturer Part Number: TS8388BMFSB_Q
• Description: ADC 8-bit 1 Gsps.
• Manufacturer: Atmel Corporation

Table 8. TS8388BF/TS8388BFS Pin Description (CQFP68 package)
Notes:
2144C–BDC–04/03
Symbol
GND
V
V
V
DV
V
V
CLK
CLKB
D0, D1, D2, D3, D4,
D5, D6, D7
D0B, D1B, D2B, D3B,
D4B, D5B, D6B, D7B
OR
ORB
DR
DRB
GORB
GAIN
DIOD/DRRB
PLUSD
CC
EE
IN
INB
EE
1. Following pin numbers 37 (CLK), 40 (CLKB), 54 (V
2. The common mode level of the output buffers is 1.2V below the positive digital supply.
close as possible to the package (50 termination preferred option).
For ECL compatibility the positive digital supply must be set at 0V (ground).
For LVDS compatibility (output common mode at +1.2V) the positive digital supply must be set at 2.4V.
If the subsequent LVDS circuitry can withstand a lower level for input common mode, it is recommended to lower the posi-
tive digital supply level in the same proportion in order to spare power dissipation.
Pin number
5, 13, 27, 28, 34, 35, 36, 41, 42, 43, 50, 51,
52, 53, 58, 59
1, 2, 16, 17, 18, 68
26, 29, 32, 33, 46, 47, 61
30, 31, 44, 45, 48
8, 9, 10
54
56, 57
37
39, 40
23, 21, 19, 14, 6, 3, 66, 64
24, 22, 20, 15, 7, 4, 67, 65
62
63
11
12
25
60
49
(1)
(1)
, 55
, 38
(1)
(1)
IN
) and 57 (V
Function
Ground pins.
To be connected to external ground plane.
Digital positive supply (0V for ECL compatibility, 2.4V for
LVDS compatibility).
+5V positive supply.
-5V analog negative supply.
-5V digital negative supply.
In phase (+) analog input signal of the Sample and Hold
differential preamplifier.
Inverted phase (-) of analog input signal (V
In phase (+) ECL clock input signal. The analog input is
sampled and held on the rising edge of the CLK signal.
Inverted phase (-) of ECL clock input signal (CLK).
In phase (+) digital outputs.
B0 is the LSB. B7 is the MSB.
Inverted phase (-) digital outputs.
B0B is the inverted LSB. B7B is the inverted MSB.
In phase (+) Out of Range Bit. Out of Range is high on the
leading edge of code 0 and code 256.
Inverted phase (+) Out of Range Bit (OR).
In phase (+) output of Data Ready Signal.
Inverted phase (-) output of Data Ready Signal (DR).
Gray or Binary select output format control pin.
- Binary output format if GORB is floating or V
- Gray output format if GORB is connected at ground (0V).
ADC gain adjust pin.
This pin has a double function (can be left open or grounded
if not used):
- DIOD: die junction temperature monitoring pin.
- DRRB: asynchronous data ready reset function.
INB
) have to be connected to GND through a 50
(2)
IN
TS8388B
).
CC
.
resistor as
15