TS8388BMFSB_Q Atmel Corporation, TS8388BMFSB_Q Datasheet - Page 29

• Manufacturer Part Number: TS8388BMFSB_Q
• Description: ADC 8-bit 1 Gsps.
• Manufacturer: Atmel Corporation

Data Ready Output
Signal Restart
Analog Inputs (V
(V
Differential Inputs
Voltage Span
2144C–BDC–04/03
INB
)
IN
)
The Data Ready output signal restarts on DRRB command rising edge, ECL logical high levels
(-0.8V). DRRB may also be Grounded, or is allowed to float, for normal free running Data
Ready output signal.
The Data Ready signal restart sequence depends on the logical level of the external encoding
clock, at DRRB rising edge instant:
•
•
Consequently, as the analog input is sampled on clock rising edge, the first digitized data cor-
responding to the first acquisition (N) after Data Ready signal restart (rising edge) is always
strobed by the third rising edge of the data ready signal.
The time delay (TD1) is specified between the last point of a change in the differential output
data (zero crossing point) to the rising or falling edge of the differential Data Ready signal (DR,
DRB) (zero crossing point).
For normal initialization of Data Ready output signal, the external encoding clock signal fre-
quency and level must be controlled. It is reminded that the minimum encoding clock sampling
rate for the ADC is 10 MSPS and consequently the clock cannot be stopped.
One single pin is used for both DRRB input command and die junction temperature monitor-
ing. Pin denomination will be DRRB/DIOD. On the former version denomination was DIOD.
Temperature monitoring and Data Ready control by DRRB is not possible simultaneously.
The analog input Full Scale range is 0.5V peak to peak (Vpp), or -2 dBm into the 50 termina-
tion resistor.
In differential mode input configuration, that means 0.25V on each input, or
0V. The input common mode is GROUND.
The typical input capacitance is 3 pF for TS8388B in CQFP and CBGA packages.
The input capacitance is mainly due to the package. The ESD protections are not connected
(but present) on the inputs.
Figure 29. Differential Inputs Voltage Span
The DRRB rising edge occurs when external encoding clock input (CLK, CLKB) is LOW:
The Data Ready output first rising edge occurs after half a clock period on the clock falling
edge, after a delay time TDR = 1320 ps already defined hereabove.
The DRRB rising edge occurs when external encoding clock input (CLK, CLKB) is HIGH:
The Data Ready output first rising edge occurs after one clock period on the clock falling
edge, and a delay TDR = 1320 ps.
analog input
Full Scale
500 mV
-125
125
[mV]
(VIN, VINB) = ±250 mV = 500 mV diff
250 mV
VIN
-250 mV
VINB
0V
t
TS8388B
±
125 mV around
29