TS8388BMFSB_Q Atmel Corporation, TS8388BMFSB_Q Datasheet - Page 2

• Manufacturer Part Number: TS8388BMFSB_Q
• Description: ADC 8-bit 1 Gsps.
• Manufacturer: Atmel Corporation

Functional
Description
Block Diagram
Figure 1. Simplified Block Diagram
Functional
Description
2
CLK, CLKB
V
IN
, V
INB
TS8388B
DRRB DR, DRB
G=2
BUFFER
MASTER/SLAVE TRACK & HOLD AMPLIFIER
CLOCK
T/H
The following figure shows the simplified block diagram.
The TS8388B is an 8-bit 1 GSPS ADC based on an advanced high-speed bipolar technology
featuring a cutoff frequency of 25 GHz.
The TS8388B includes a front-end master/slave Track and Hold stage (S/H), followed by an
analog encoding stage and interpolation circuitry.
Successive banks of latches regenerate the analog residues into logical data before entering
an error correction circuitry and a resynchronization stage followed by 75
buffers.
The TS8388B works in fully differential mode from analog inputs up to digital outputs.
The TS8388B features a full-power input bandwidth of 1.5 GHz.
A control pin GORB is provided to select either Gray or Binary data output format.
A gain control pin is provided in order to adjust the ADC gain.
A Data Ready output asynchronous reset (DRRB) is available on TS8388B.
The TS8388B uses only vertical isolated NPN transistors together with oxide isolated polysili-
con resistors, which allow enhanced radiation tolerance (no performance drift measured at
150 kRad total dose).
G=1
T/H
G=1
RESISTOR
CHAIN
GAIN
ENCODING
ANALOG
BLOCK
GORB
4
4
4
DATA, DATAB OR, ORB
ERROR CORRECTION &
OUTPUT LATCHES &
8
INTERPOLATION
REGENERATION
DECODE LOGIC
BUFFERS
LATCHES
STAGES
8
differential output
2144C–BDC–04/03
5
5