TS8388BMFSB_Q Atmel Corporation, TS8388BMFSB_Q Datasheet - Page 13

• Manufacturer Part Number: TS8388BMFSB_Q
• Description: ADC 8-bit 1 Gsps.
• Manufacturer: Atmel Corporation

Package
Description
Pin Description
Table 7. TS8388BGL Pin Description (CBGA68 package)
Note:
2144C–BDC–04/03
Symbol
GND
V
V
DV
V
V
CLK
CLKB
B0, B1, B2, B3, B4,
B5, B6, B7
B0B, B1B, B2B, B3B,
B4B, B5B, B6B, B7B
OR
ORB
DR
DRB
GORB
GAIN
DIOD/DRRB
V
NC
CC
EE
IN
INB
PLUSD
EE
1. The common mode level of the output buffers is 1.2V below the positive digital supply.
For ECL compatibility the positive digital supply must be set at 0V (ground).
For LVDS compatibility (output common mode at +1.2V) the positive digital supply must be set at 2.4V.
If the subsequent LVDS circuitry can withstand a lower level for input common mode, it is recommended to lower the posi-
tive digital supply level in the same proportion in order to spare power dissipation.
Pin number
A2, A5, B1, B5, B10, C2, D2, E1, E2, E11,
F1, F2, G11, K2, K3, K4, K5, K10, L2, L5
A4, A6, B2, B4, B6, H1, H2, L6, L7
A3, B3, G1, G2, J1, J2
F10, F11
L3
L4
C1
D1
A8, A9, A10, D10, H11, J11, K9, K8
B7, B8, B9, C11, G10, H10, L10, L9
K7
L8
E10
D11
A7
K6
K1
B11, C10, J10, K11
A1, A11, L1, L11
Function
Ground pins.
To be connected to external ground plane.
+5V positive supply.
5V analog negative supply.
-5V digital negative supply.
In phase (+) analog input signal of the Sample and Hold
differential preamplifier.
Inverted phase (-) of ECL clock input signal (CLK).
In phase (+) ECL clock input signal. The analog input is
sampled and held on the rising edge of the CLK signal.
Inverted phase (-) of ECL clock input signal (CLK).
In phase (+) digital outputs.
B0 is the LSB. B7 is the MSB.
Inverted phase (-) digital outputs.
B0B is the inverted LSB. B7B is the inverted MSB.
In phase (+) Out of Range Bit. Out of Range is high on the
leading edge of code 0 and code 256.
Inverted phase (+) Out of Range Bit (OR).
In phase (+) output of Data Ready Signal.
Inverted phase (-) output of Data Ready Signal (DR).
Gray or Binary select output format control pin.
- Binary output format if GORB is floating or V
- Gray output format if GORB is connected at ground (0V).
ADC gain adjust pin. The gain pin is by default grounded, the
ADC gain transfer fuction is nominally close to one.
Die function temperature measurement pin and
asynchronous data ready reset active low, single-ended ECL
input.
+2.4V for LVDS output levels otherwise to GND
Not connected.
TS8388B
CC
(2)
.
.
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