TS8388BMFSB_Q Atmel Corporation, TS8388BMFSB_Q Datasheet - Page 6

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TS8388BMFSB_Q

Manufacturer Part Number
TS8388BMFSB_Q
Description
ADC 8-bit 1 Gsps.
Manufacturer
Atmel Corporation
Datasheet
Table 3. Electrical Specifications (Continued)
6
Parameter
Digital Outputs
Single-ended or differential input mode, 50% clock duty cycle (CLK, CLKB), Binary output data format,
Tj (typical) = 70 C.
Logic compatibility for digital outputs
(Depending on the value of V
(See Application Notes)
Differential output voltage swings
(assuming V
Output levels (assuming V
75 open transmission lines:
Output levels (assuming V
75 differentially terminated:
Output levels (assuming V
50 differentially terminated:
Differential Output Swing
Output level drift with temperature
DC Accuracy (CBGA68 package)
Single-ended or differential input mode, 50% clock duty cycle (CLK, CLKB), Binary output data format
Tj (typical) = 70 C.
Differential non linearity
Differential non linearity
Integral non linearity
Integral non linearity
No missing codes
Gain
Input offset voltage
75 open transmission lines (ECL levels)
75 differentially terminated
50 differentially terminated
Logic “0” voltage
Logic “1” voltage
Logic “0” voltage
Logic “1” voltage
Logic “0” voltage
Logic “1” voltage
TS8388B
PLUSD
= 0V):
PLUSD
PLUSD
PLUSD
PLUSD
= 0V)
= 0V)
= 0V)
)
Symbol
DNL+
DNL-
DOS
INL+
INL-
V
V
V
V
V
V
OH
OH
OH
OL
OL
OL
Level
Test
1, 2
1, 2
1, 2
1, 2
4
4
4
6
6
4
4
1
1
1
1
Guaranteed over specified temperature range
-0.88
-1.07
-1.16
-1.25
0.70
0.54
Min
270
-0.6
-1.2
1.5
-26
90
ECL or LVDS
Value
0.825
0.660
1.620
-1.62
-1.41
-1.40
-1.40
-1.10
-1.10
Typ
-0.8
-0.4
-0.7
300
0.4
0.7
98
-1
-5
-1.54
-1.34
-1.32
-1.25
Max
110
1.6
0.6
1.2
26
mV/ C
Unit
mV
mV
lsb
lsb
lsb
lsb
%
V
V
V
V
V
V
V
V
V
V
V
2144C–BDC–04/03
Note
(1)(6)
(2)(3)
(2)(3)
(6)
(6)
(6)
(3)

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