TS8388BMFSB_Q Atmel Corporation, TS8388BMFSB_Q Datasheet - Page 48

• Manufacturer Part Number: TS8388BMFSB_Q
• Description: ADC 8-bit 1 Gsps.
• Manufacturer: Atmel Corporation

Definitions
Definition of
Terms
(BER) Bit Error Rate
(FPBW) Full Power
Input Bandwidth
(SINAD) Signal to Noise
and Distortion Ratio
(SNR) Signal to Noise
Ratio
(THD) Total Harmonic
Distorsion
(SFDR) Spurious Free
Dynamic Range
(ENOB) Effective
Number Of Bits
(DNL) Differential Non
Linearity
(INL) Integral Non
Linearity
(DG) Differential Gain
(DP) Differential Phase
(TA) Aperture Delay
48
TS8388B
Probability to exceed a specified error threshold for a sample. An error code is a code that dif-
fers by more than
Analog input frequency at which the fundamental component in the digitally reconstructed out-
put has fallen by 3 dB with respect to its low frequency value (determined by FFT analysis) for
input at Full Scale.
Ratio expressed in dB of the RMS signal amplitude, set to 1 dB below Full Scale, to the RMS
sum of all other spectral components, including the harmonics except DC.
Ratio expressed in dB of the RMS signal amplitude, set to 1 dB below Full Scale, to the RMS
sum of all other spectral components excluding the five first harmonics.
Ratio expressed in dBc of the RMS sum of the first five harmonic components, to the RMS
value of the measured fundamental spectral component.
Ratio expressed in dB of the RMS signal amplitude, set at 1 dB below Full Scale, to the RMS
value of the next highest spectral component (peak spurious spectral component). SFDR is
the key parameter for selecting a converter to be used in a frequency domain application
(Radar systems, digital receiver, network analyzer, etc.). It may be reported in dBc (i.e.:
degrades as signal levels is lowered), or in dBFS (i.e.: always related back to converter full
scale).
Where A is the actual input amplitude and V is the full scale range of the ADC under test.
The Differential Non Linearity for an output code i is the difference between the measured step
size of code i and the ideal LSB step size. DNL (i) is expressed in LSBs. DNL is the maximum
value of all DNL (i). DNL error specification of less than 1 lsb guarantees that there are no
missing output codes and that the transfer function is monotonic.
The Integral Non Linearity for an output code i is the difference between the measured input
voltage at which the transition occurs and the ideal value of this transition.
INL (i) is expressed in LSBs, and is the maximum value of all |INL (i)|.
The peak gain variation (in percent) at five different DC levels for an AC signal of 20% Full
Scale peak to peak amplitude. F
Peak Phase variation (in degrees) at five different DC levels for an AC signal of 20% Full
Scale peak to peak amplitude. F
Delay between the rising edge of the differential clock inputs (CLK, CLKB) (zero crossing
point), and the time at which (V
ENOB =
SINAD - 1.76 + 20 log (A/V/2)
±
4 lsb from the correct code.
6.02
IN
IN
IN
, V
= 5 MHz (TBC).
= 5 MHz (TBC).
INB
) is sampled.
2144C–BDC–04/03