TS8388BMFSB_Q Atmel Corporation, TS8388BMFSB_Q Datasheet - Page 49

• Manufacturer Part Number: TS8388BMFSB_Q
• Description: ADC 8-bit 1 Gsps.
• Manufacturer: Atmel Corporation

(JITTER) Aperture
Uncertainty
(TS) Settling Time
(ORT) Overvoltage
Recovery Time
(TOD) Digital Data
Output Delay
(TD1) Time Delay from
Data to Data Ready
(TD2) Time Delay from
Data Ready to Data
(TC) Encoding Clock
Period
(TPD) Pipeline Delay
(TRDR) Data Ready
Reset Delay
(TR) Rise Time
(TF) Fall Time
(PSRR) Power Supply
Rejection Ratio
(NRZ) Non Return to
Zero
(IMD) InterModulation
Distortion
(NPR) Noise Power
Ratio
2144C–BDC–04/03
Sample to sample variation in aperture delay. The voltage error due to jitter depends on the
slew rate of the signal at the sampling point.
Time delay to achieve 0.2% accuracy at the converter output when a 80% Full Scale step
function is applied to the differential analog input.
Time to recover 0.2% accuracy at the output, after a 150% full scale step applied on the input
is reduced to midscale.
Delay from the falling edge of the differential clock inputs (CLK, CLKB) (zero crossing point) to
the next point of change in the differential output data (zero crossing) with specified load.
Time delay from Data transition to Data ready.
General expression is TD1 = TC1 + TDR - TOD with TC = TC1 + TC2 = 1 encoding clock
period.
TC1 = Minimum clock pulse width (high) TC = TC1 + TC2
TC2 = Minimum clock pulse width (low)
Number of clock cycles between the sampling edge of an input data and the associated output
data being made available, (not taking in account the TOD). For the TS8388B the TPD is 4
clock periods.
Delay between the falling edge of the Data Ready output asynchronous Reset signal (DDRB)
and the reset to digital zero transition of the Data Ready output signal (DR).
Time delay for the output DATA signals to rize from 20% to 80% of delta between low level
and high level.
Time delay for the output DATA signals to fall from 80% to 20% of delta between low level and
high level.
Ratio of input offset variation to a change in power supply voltage.
When the input signal is larger than the upper bound of the ADC input range, the output code
is identical to the maximum code and the Out of Range bit is set to logic one. When the input
signal is smaller than the lower bound of the ADC input range, the output code is identical to
the minimum code, and the Out of range bit is set to logic one. (It is assumed that the input sig-
nal amplitude remains within the absolute maximum ratings).
The two tones intermodulation distortion (IMD) rejection is the ratio of either input tone to the
worst third order intermodulation products. The input tones levels are at -7 dB Full Scale.
The NPR is measured to characterize the ADC performance in response to broad bandwidth
signals. When using a notch-filtered broadband white-noise generator as the input to the ADC
under test, the Noise Power Ratio is defined as the ratio of the average out-of-notch to the
average in-notch power spectral density magnitudes for the FFT spectrum of the ADC output
sample test.
TS8388B
49