TS8388BMFSB_Q Atmel Corporation, TS8388BMFSB_Q Datasheet - Page 30

• Manufacturer Part Number: TS8388BMFSB_Q
• Description: ADC 8-bit 1 Gsps.
• Manufacturer: Atmel Corporation

Differential Versus
Single-ended Analog
Input Operation
Typical Single-ended
Analog Input
Configuration
Figure 30. Typical Single-ended Analog Input Configuration
Note:
Clock Inputs (CLK)
(CLKB)
Single-ended Clock
Input (Ground
Common Mode)
30
analog input
Since VIN and VINB have a double pad architecture, a 50 reverse termination is needed. For the CBGA package, this reverse
termination is already on package.
Full Scale
TS8388B
500 mV
-250
250
[mV]
500 mV
VIN = ±250 mV = 500 mV diff
The TS8388B can operate at full speed in either differential or single-ended configuration.
This is explained by the fact the ADC uses a high input impedance differential preamplifier
stage, (preceeding the Sample and hold stage), which has been designed in order to be
entered either in differential mode or single-ended mode.
This is true so long as the out-of-phase analog input pin V
one of the neighboring shield ground pins (52, 53, 58, 59) which constitute the local ground
reference for the inphase analog input pin (V
Thus the differential analog input preamplifier will fully reject the local ground noise (and any
capacitively and inductively coupled noise) as common mode effects.
In typical single-ended configuration, enter on the (V
pin (V
In single-ended input configuration, the in-phase input amplitude is 0.5V peak to peak, cen-
tered on 0V (or -2 dBm into 50 ). The inverted phase input is at ground potential through a
50 termination resistor.
However, dynamic performances can be somewhat improved by entering either analog or
clock inputs in differential mode.
The TS8388B can be clocked at full speed without noticeable performance degradation in
either differential or single-ended configuration.
This is explained by the fact the ADC uses a differential preamplifier stage for the clock buffer,
which has been designed in order to be entered either in differential or single-ended mode.
Recommended sinewave generator characteristics are typically -120 dBc/Hz phase noise floor
spectral density, at 1 kHz from carrier, assuming a single tone 4 dBm input for the clock signal.
Although the clock inputs were intended to be driven differentially with nominal -0.8V/-1.8V
ECL levels, the TS8388B clock buffer can manage a single-ended sinewave clock signal cen-
tered around 0V. This is the most convenient clock input configuration as it does not require
the use of a power splitter.
VIN
INB
) grounded through the 50
VINB
VINB = 0V
t
termination resistor.
on package)
(external or
IN
).
VIN or VINB double pad (pins 54, 55 or 56, 57)
VIN or VINB
50Ω
IN
) input pin, with the inverted phase input
INB
50Ω reverse termination
is 50 terminated very closely to
1 MΩ
2144C–BDC–04/03
3 pF