cy2sstu32864 SpectraLinear Inc, cy2sstu32864 Datasheet - Page 2

• Manufacturer Part Number: cy2sstu32864
• Description: 1.8v, 25-bit 14-bit Jedec-compliant Data Register
• Manufacturer: SpectraLinear Inc

Rev 1.0, November 25, 2006
Pin Definitions
GND
VDD
VREF
ZOH
ZOL
CK
CK#
C0
C1
RESET#
CSR#
DCS#
D1
D2-3
D4
D5, 6, 8, 9,
10
D11
D12, 13
D14
D15-25
DODT
DCKE
Q1A
Q2A–3A
Q4A
Q5A, 6A, 8A,
9A, 10A
Q11A
Pin Name
B3, B4, D3, D4, F3, F4,
H3, H4, K3, K4, M3, M4,
P3, P4
A4, C3, C4, E3, E4, G3,
G4, J3, J4, L3, L4, N3,
N4, R3, R4, T4
A3, T3
J5
J6
H1
J1
G6
G5
G2
J2
H2
B1, C1
E1, F1, K1, L1, M1
N1
P1, R1
T1
B2, C2, E2, F2, K2, L2,
M2, N2, P2, R2, T2
D1
A1
B5, C5
E5, F5, K5, L5, M5
N5
(C0 = 0, C1 = 0)
Pin Number
B3, B4, D3, D4, F3,
F4, H3, H4, K3, K4,
M3, M4, P3, P4
A4, C3, C4, E3,
E4, G3, G4, J3, J4,
L3, L4, N3, N4, R3,
R4, T4
A3, T3
J5
J6
H1
J1
G6
G5
G2
J2
H2
B1, C1
E1, F1, K1, L1, M1 E1, F1, K1, L1, M1 Data Input – clocked in on the crossing points of
N1
P1, R1
T1
D1
A1
B5, C5
E5, F5, K5, L5, M5 E5, F5, K5, L5, M5 Data Outputs that are suspended by the DCS#
N5
(C0 = 0, C1 = 1)
Pin Number
B3, B4, D3, D4, F3,
F4, H3, H4, K3, K4,
M3, M4, P3, P4
A4, C3, C4, E3,
E4, G3, G4, J3, J4,
L3, L4, N3, N4, R3,
R4, T4
A3, T3
J5
J6
H1
J1
G6
G5
G2
J2
H2
A1
B1, C1
D1
P1, R1
N1
T1
A5
B5, C5
D5
(C0 = 1, C1 = 1)
Pin Number
Ground
Power Supply Voltage
Input Reference Voltage
Reserved
Reserved
Positive Master Clock
Negative Master Clock
Configuration Control Input
Configuration Control Input
Asynchronous Reset – resets registers and
disables Vref data and clock differential input
receivers
Chip Select – Disables D1-D24 when both CSR#
and DCS# are High (VDD)
Chip Select – Disables D1-D24 when both CSR#
and DCS# are High (VDD)
Data Input – clocked in on the crossing points of
CK and CK#
Data Input – clocked in on the crossing points of
CK and CK#
Data Input – clocked in on the crossing points of
CK and CK#
CK and CK#
Data Input – clocked in on the crossing points of
CK and CK#
Data Input – clocked in on the crossing points of
CK and CK#
Data Input – clocked in on the crossing points of
CK and CK#
Data Input – clocked in on the crossing points of
CK and CK#
The outputs of this register bit will not be
suspended by the DCS# and CSR# Control
The outputs of this register bit will not be
suspended by the DCS# and CSR# Control
Data Outputs that are suspended by the DCS#
and CSR# control
Data Outputs that are suspended by the DCS#
and CSR# control
Data Outputs that are suspended by the DCS#
and CSR# control
and CSR# control
CY2SSTU32864
Description
Page 2 of 9