mt48lc16m4a2tg Micron Semiconductor Products, mt48lc16m4a2tg Datasheet - Page 11

• Manufacturer Part Number: mt48lc16m4a2tg
• Description: 64mb X4, X8, X16 Sdram
• Manufacturer: Micron Semiconductor Products

Commands
available commands. This is followed by a written de-
scription of each command. Three additional Truth
NOTE: 1. CKE is HIGH for all commands shown except SELF REFRESH.
TRUTH TABLE 1 – COMMANDS AND DQM OPERATION
(Note: 1)
64Mb: x4, x8, x16 SDRAM
64MSDRAM_F.p65 – Rev. F; Pub. 1/03
NAME (FUNCTION)
COMMAND INHIBIT (NOP)
NO OPERATION (NOP)
ACTIVE (Select bank and activate row)
READ (Select bank and column, and start READ burst)
WRITE (Select bank and column, and start WRITE burst)
BURST TERMINATE
PRECHARGE (Deactivate row in bank or banks)
AUTO REFRESH or SELF REFRESH
(Enter self refresh mode)
LOAD MODE REGISTER
Write Enable/Output Enable
Write Inhibit/Output High-Z
Truth Table 1 provides a quick reference of
2. A0-A11 define the op-code written to the mode register.
3. A0-A11 provide row address, and BA0, BA1 determine which bank is made active.
4. A0-A9 (x4), A0-A8 (x8), or A0-A7 (x16) provide column address; A10 (HIGH) enables the auto precharge feature
5. A10 (LOW): BA0, BA1 determine the bank being precharged. A10 HIGH: All banks precharged and BA0, BA1 are “Don’t
6. This command is AUTO REFRESH if CKE is (HIGH), SELF REFRESH if CKE is LOW.
7. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for CKE.
8. Activates or deactivates the DQs during WRITEs (zero-clock delay) and READs (two-clock delay).
(nonpersistent), while A10 (LOW) disables the auto precharge feature; BA0, BA1 determine which bank is being read
from or written to.
Care.”
11
CS# RAS# CAS# WE# DQM
H
L
L
L
L
L
L
L
–
–
L
Tables appear following the Operation section; these
tables provide current state/next state information.
X
H
H
H
H
L
L
L
–
–
L
Micron Technology, Inc., reserves the right to change products or specifications without notice.
H
H
H
H
X
L
L
L
L
–
–
H
H
H
H
X
L
L
L
L
–
–
L/H
L/H
X
X
X
X
X
X
X
H
L
64Mb: x4, x8, x16
8
8
Bank/Row
Bank/Col
Bank/Col
Op-Code
ADDR
Code
X
X
X
X
–
–
High-Z
Active
Active
©2003, Micron Technology, Inc.
Valid
DQs NOTES
SDRAM
X
X
X
X
X
X
X
6, 7
3
4
4
5
2
8
8