mt48lc16m4a2tg Micron Semiconductor Products, mt48lc16m4a2tg Datasheet - Page 35

• Manufacturer Part Number: mt48lc16m4a2tg
• Description: 64mb X4, X8, X16 Sdram
• Manufacturer: Micron Semiconductor Products

NOTES
1. All voltages referenced to V
2. This parameter is sampled. V
3. I
4. Enables on-chip refresh and address counters.
5. The minimum specifications are used only to
6. An initial pause of 100µs is required after power-
7. AC characteristics assume
8. In addition to meeting the transition rate specifi-
9. Outputs measured at 1.5V with equivalent load:
10.
11. AC timing and I
12. Other input signals are allowed to transition no
64Mb: x4, x8, x16 SDRAM
64MSDRAM_F.p65 – Rev. F; Pub. 1/03
f = 1 MHz, T
Specified values are obtained with minimum cycle
time and the outputs open.
indicate cycle time at which proper operation over
the full temperature range (0°C £ T
-40°C £ T
up, followed by two AUTO REFRESH commands,
before proper device operation is ensured. (V
and V
and V
AUTO REFRESH command wake-ups should be
repeated any time the
exceeded.
cation, the clock and CKE must transit between V
and V
manner.
t
the open circuit condition; it is not a reference to
V
t
with timing referenced to 1.5V crossover point. If
the input transition time is longer than 1 ns, then
the timing is referenced at V
and no longer at the 1.5V crossover point. CLK
should always be 1.5V referenced to crossover. Re-
fer to Micron Technical Note TN-48-09
more than once every two clocks and are otherwise
at valid V
HZ defines the time at which the output achieves
OH before going High-Z.
DD
OH
is dependent on output loading and cycle rates.
or V
DD
IL
SS
Q must be powered up simultaneously. V
Q must be at same potential.) The two
(or between V
OL
A
IH
. The last valid data element will meet
£ +85°C for IT parts) is ensured.
or V
A
= 25°C; pin under test biased at 1.4V.
Q
DD
IL
levels.
tests have V
t
IL
REF refresh requirement is
and V
t
T = 1ns.
SS
IL
.
(MAX) and V
IL
IH
DD
= 0V and V
50pF
) in a monotonic
, V
A
DD
£ +70°C and
Q = +3.3V;
IH
IH
(MIN)
= 3V,
DD
IH
SS
35
13. I
14. Timing actually specified by
15. Timing actually specified by
16. Timing actually specified by
17. Required clocks are specified by JEDEC function-
18. The I
19. Address transitions average one transition every
20. CLK must be toggled a minimum of two times dur-
21. Based on
22. V
23. The clock frequency must remain constant (stable
24. Auto precharge mode only. The precharge timing
25. Precharge mode only.
26. JEDEC and PC100 specify three clocks.
27.
28. Parameter guaranteed by design.
29. PC100 specifies a maximum of 4pF.
30. PC100 specifies a maximum of 5pF.
31. PC100 specifies a maximum of 6.5pF.
32. For -8E, CL = 2 and
33. CKE is HIGH during refresh command period
erly initialized.
fied as a reference only at minimum cycle rate.
specified as a reference only at minimum cycle rate.
ality and are not dependent on any timing param-
eter.
tionally according to the amount of frequency al-
teration for the test condition.
two clocks.
ing this period.
and -7E,
width £ 3ns, and the pulse width cannot be greater
than one third of the cycle rate. V
(MIN) = -2V for a pulse width £ 3ns.
clock is defined as a signal cycling within timing
constraints specified for the clock pin) during ac-
cess or precharge states (READ, WRITE, including
t
used to reduce the data rate.
budget (
first clock delay, after the last WRITE is executed.
t
guaranteed by design.
t
CL = 3 and
t
ally a nominal value and does not result in a fail
value.
WR, and PRECHARGE commands). CKE may be
AC for -75/-7E at CL = 3 with no load is 4.6ns and is
CK = 7.5ns; for -7E, CL = 2 and
RFC (MIN) else CKE is LOW. The I
DD
IH
specifications are tested after the device is prop-
overshoot: V
DD
Micron Technology, Inc., reserves the right to change products or specifications without notice.
current will increase or decrease propor-
t
t
CK = 6ns for -6.
RP) begins 6ns/7ns/7.5ns/7ns after the
t
CK = 10ns for -8E ,
t
CK = 6ns.
IH
(MAX) = V
64Mb: x4, x8, x16
t
CK = 10ns; for -75, CL = 3 and
t
t
WR plus
DD
t
WR.
CKS; clock(s) speci-
Q + 2V for a pulse
t
t
CK = 7.5ns; for -6,
CK=7.5ns for -75
IL
DD
undershoot: V
©2003, Micron Technology, Inc.
6 limit is actu-
SDRAM
t
RP; clock(s)
IL