mt48lc16m4a2tg Micron Semiconductor Products, mt48lc16m4a2tg Datasheet - Page 12

• Manufacturer Part Number: mt48lc16m4a2tg
• Description: 64mb X4, X8, X16 Sdram
• Manufacturer: Micron Semiconductor Products

COMMAND INHIBIT
commands from being executed by the SDRAM, re-
gardless of whether the CLK signal is enabled. The
SDRAM is effectively deselected. Operations already
in progress are not affected.
NO OPERATION (NOP)
perform a NOP to an SDRAM which is selected (CS# is
LOW). This prevents unwanted commands from being
registered during idle or wait states. Operations already
in progress are not affected.
LOAD MODE REGISTER
mode register heading in the Register Definition section.
The LOAD MODE REGISTER command can only be is-
sued when all banks are idle, and a subsequent execut-
able command cannot be issued until
ACTIVE
a row in a particular bank for a subsequent access. The
value on the BA0, BA1 inputs selects the bank, and the
address provided on inputs A0-A11 selects the row.
This row remains active (or open) for accesses until a
PRECHARGE command is issued to that bank.
A PRECHARGE command must be issued before open-
ing a different row in the same bank.
READ
access to an active row. The value on the BA0, BA1
inputs selects the bank, and the address provided on
inputs A0-A9 (x4), A0-A8 (x8), or A0-A7 (x16) selects the
starting column location. The value on input A10 de-
termines whether or not auto precharge is used. If auto
precharge is selected, the row being accessed will be
precharged at the end of the READ burst; if auto
precharge is not selected, the row will remain open for
subsequent accesses. Read data appears on the DQs
subject to the logic level on the DQM inputs two clocks
earlier. If a given DQM signal was registered HIGH, the
corresponding DQs will be High-Z two clocks later; if
the DQM signal was registered LOW, the DQs will pro-
vide valid data.
WRITE
access to an active row. The value on the BA0, BA1
inputs selects the bank, and the address provided on
inputs A0-A9 (x4), A0-A8 (x8), or A0-A7 (x16) selects the
starting column location. The value on input A10 de-
termines whether or not auto precharge is used. If auto
64Mb: x4, x8, x16 SDRAM
64MSDRAM_F.p65 – Rev. F; Pub. 1/03
The COMMAND INHIBIT function prevents new
The NO OPERATION (NOP) command is used to
The mode register is loaded via inputs A0-A11. See
The ACTIVE command is used to open (or activate)
The READ command is used to initiate a burst read
The WRITE command is used to initiate a burst write
t
MRD is met.
12
precharge is selected, the row being accessed will be
precharged at the end of the WRITE burst; if auto
precharge is not selected, the row will remain open for
subsequent accesses. Input data appearing on the DQs
is written to the memory array subject to the DQM in-
put logic level appearing coincident with the data. If a
given DQM signal is registered LOW, the correspond-
ing data will be written to memory; if the DQM signal is
registered HIGH, the corresponding data inputs will
be ignored, and a WRITE will not be executed to that
byte/column location.
PRECHARGE
the open row in a particular bank or the open row in all
banks. The bank(s) will be available for a subsequent
row access a specified time (
command is issued. Input A10 determines whether
one or all banks are to be precharged, and in the case
where only one bank is to be precharged, inputs BA0,
BA1 select the bank. Otherwise BA0, BA1 are treated as
“Don’t Care.” Once a bank has been precharged, it is in
the idle state and must be activated prior to any READ
or WRITE commands being issued to that bank.
AUTO PRECHARGE
same individual-bank PRECHARGE function de-
scribed above, without requiring an explicit command.
This is accomplished by using A10 to enable auto
precharge in conjunction with a specific READ or WRITE
command. A precharge of the bank/row that is ad-
dressed with the READ or WRITE command is auto-
matically performed upon completion of the READ or
WRITE burst, except in the full-page burst mode, where
auto precharge does not apply. Auto precharge is non-
persistent in that it is either enabled or disabled for
each individual READ or WRITE command.
ated at the earliest valid stage within a burst. The user
must not issue another command to the same bank
until the precharge time (
determined as if an explicit PRECHARGE command
was issued at the earliest possible time, as described
for each burst type in the Operation section of this data
sheet.
BURST TERMINATE
cate either fixed-length or full-page bursts. The most
recently registered READ or WRITE command prior to
the BURST TERMINATE command will be truncated,
as shown in the Operation section of this data sheet.
The PRECHARGE command is used to deactivate
Auto precharge is a feature which performs the
Auto precharge ensures that the precharge is initi-
The BURST TERMINATE command is used to trun-
Micron Technology, Inc., reserves the right to change products or specifications without notice.
64Mb: x4, x8, x16
t
t
RP) is completed. This is
RP) after the PRECHARGE
©2003, Micron Technology, Inc.
SDRAM