mt48lc16m4a2tg Micron Semiconductor Products, mt48lc16m4a2tg Datasheet - Page 25

• Manufacturer Part Number: mt48lc16m4a2tg
• Description: 64mb X4, X8, X16 Sdram
• Manufacturer: Micron Semiconductor Products

CONCURRENT AUTO PRECHARGE
bank while an access command with auto precharge
enabled is executing is not allowed by SDRAMs, unless
the
PRECHARGE. Micron SDRAMs support CONCURRENT
AUTO PRECHARGE. Four cases where CONCURRENT
AUTO PRECHARGE occurs are defined below.
READ with Auto Precharge
1. Interrupted by a READ (with or without auto
64Mb: x4, x8, x16 SDRAM
64MSDRAM_F.p65 – Rev. F; Pub. 1/03
An access command (READ or WRITE) to another
precharge): A READ to bank m will interrupt a READ
SDRAM
supports
READ With Auto Precharge Interrupted by a WRITE
READ With Auto Precharge Interrupted by a READ
Internal
States
NOTE: 1. DQM is HIGH at T2 to prevent D
Internal
States
NOTE: DQM is LOW.
CONCURRENT
COMMAND
ADDRESS
COMMAND
BANK m
BANK n
ADDRESS
BANK m
BANK n
CLK
DQ
DQM
CLK
DQ
1
Active
Page
Page Active
T0
NOP
READ - AP
BANK n,
BANK n
COL a
T0
READ with Burst of 4
CAS Latency = 3 (BANK n)
READ - AP
BANK n,
Page Active
BANK n
COL a
T1
Page Active
AUTO
T1
NOP
READ with Burst of 4
CAS Latency = 3 (BANK n)
OUT
Figure 25
Figure 24
-a+1 from contending with D
T2
NOP
T2
NOP
25
BANK m,
READ - AP
T3
BANK m
COL d
2. Interrupted by a WRITE (with or without auto
T3
Interrupt Burst, Precharge
D
NOP
CAS Latency = 3 (BANK m)
OUT
READ with Burst of 4
a
on bank n, CAS latency later. The PRECHARGE to
bank n will begin when the READ to bank m is regis-
tered (Figure 24).
precharge): A WRITE to bank m will interrupt a READ
on bank n when registered. DQM should be used
two clocks prior to the WRITE command to prevent
bus contention. The PRECHARGE to bank n will
begin when the WRITE to bank m is registered
(Figure 25).
TRANSITIONING DATA
BANK m,
T4
WRITE - AP
TRANSITIONING DATA
NOP
COL d
BANK m
T4
D
IN
D
d
IN
Interrupt Burst, Precharge
OUT
a
-d at T4.
t
WRITE with Burst of 4
RP - BANK n
Micron Technology, Inc., reserves the right to change products or specifications without notice.
T5
NOP
T5
d + 1
NOP
D
D
a + 1
IN
OUT
t
RP - BANK n
T6
NOP
T6
d + 2
NOP
D
D
IN
OUT
d
64Mb: x4, x8, x16
DON’T CARE
DON’T CARE
Idle
T7
NOP
t RP - BANK m
T7
t WR - BANK m
d + 3
NOP
D
Precharge
D
d + 1
IN
OUT
Write-Back
Idle
©2003, Micron Technology, Inc.
SDRAM