mt48lc16m4a2tg Micron Semiconductor Products, mt48lc16m4a2tg Datasheet - Page 2

• Manufacturer Part Number: mt48lc16m4a2tg
• Description: 64mb X4, X8, X16 Sdram
• Manufacturer: Micron Semiconductor Products

64Mb SDRAM PART NUMBERS
GENERAL DESCRIPTION
dynamic
67,108,864 bits. It is internally configured as a quad-
bank DRAM with a synchronous interface (all signals
are registered on the positive edge of the clock signal,
CLK). Each of the x4’s 16,777,216-bit banks is orga-
nized as 4,096 rows by 1,024 columns by 4 bits. Each of
the x8’s 16,777,216-bit banks is organized as 4,096 rows
by 512 columns by 8 bits. Each of the x16’s 16,777,216-
bit banks is organized as 4,096 rows by 256 columns by
16 bits.
oriented; accesses start at a selected location and con-
tinue for a programmed number of locations in a pro-
grammed sequence. Accesses begin with the
registration of an ACTIVE command, which is then fol-
lowed by a READ or WRITE command. The address bits
registered coincident with the ACTIVE command are
used to select the bank and row to be accessed (BA0,
BA1 select the bank; A0-A11 select the row). The ad-
64Mb: x4, x8, x16 SDRAM
64MSDRAM_F.p65 – Rev. F; Pub. 1/03
PART NUMBER
MT48LC16M4A2TG
MT48LC8M8A2TG
MT48LC4M16A2TG
The Micron
Read and write accesses to the SDRAM are burst
random-access
®
64Mb SDRAM is a high-speed CMOS,
ARCHITECTURE
16 Meg x 4
4 Meg x 16
8 Meg x 8
memory
containing
2
dress bits registered coincident with the READ or WRITE
command are used to select the starting column loca-
tion for the burst access.
WRITE burst lengths of 1, 2, 4, or 8 locations, or the
full page, with a burst terminate option. An auto
precharge function may be enabled to provide a self-
timed row precharge that is initiated at the end of the
burst sequence.
architecture to achieve high-speed operation. This
architecture is compatible with the 2n rule of prefetch
architectures, but it also allows the column address to
be changed on every clock cycle to achieve a high-
speed, fully random access. Precharging one bank
while accessing one of the other three banks will hide
the precharge cycles and provide seamless, high-
speed, random-access operation.
memory systems. An auto refresh mode is provided,
along with a power-saving, power-down mode.
All inputs and outputs are LVTTL-compatible.
ating performance, including the ability to synchro-
nously burst data at a high data rate with automatic
column-address generation, the ability to interleave
between internal banks in order to hide precharge time
and the capability to randomly change column
addresses on each clock cycle during a burst access.
The SDRAM provides for programmable READ or
The 64Mb SDRAM uses an internal pipelined
The 64Mb SDRAM is designed to operate in 3.3V
SDRAMs offer substantial advances in DRAM oper-
Micron Technology, Inc., reserves the right to change products or specifications without notice.
64Mb: x4, x8, x16
©2003, Micron Technology, Inc.
SDRAM