mt48lc16m4a2tg Micron Semiconductor Products, mt48lc16m4a2tg Datasheet - Page 24

• Manufacturer Part Number: mt48lc16m4a2tg
• Description: 64mb X4, X8, X16 Sdram
• Manufacturer: Micron Semiconductor Products

CLOCK SUSPEND
cess/burst is in progress and CKE is registered LOW. In
the clock suspend mode, the internal clock is deacti-
vated, “freezing” the synchronous logic.
sampled LOW, the next internal positive clock edge is
suspended. Any command or data present on the in-
put pins at the time of a suspended internal clock edge
is ignored; any data present on the DQ pins remains
driven; and burst counters are not incremented, as
long as the clock is suspended. (See examples in
Figures 22 and 23.)
64Mb: x4, x8, x16 SDRAM
64MSDRAM_F.p65 – Rev. F; Pub. 1/03
The clock suspend mode occurs when a column ac-
For each positive clock edge on which CKE is
Clock Suspend During WRITE Burst
COMMAND
INTERNAL
ADDRESS
CLOCK
CLK
CKE
D
IN
NOP
T0
TRANSITIONING DATA
BANK,
WRITE
COL n
Figure 22
T1
D
n
IN
T2
T3
NOP
n + 1
T4
D
IN
DON’T CARE
T5
n + 2
NOP
D
IN
24
HIGH; the internal clock and related operation will re-
sume on the subsequent positive clock edge.
BURST READ/SINGLE WRITE
gramming the write burst mode bit (M9) in the mode
register to a logic 1. In this mode, all WRITE commands
result in the access of a single column location (burst of
one), regardless of the programmed burst length. READ
commands access columns according to the pro-
grammed burst length and sequence, just as in the
normal mode of operation (M9 = 0).
COMMAND
INTERNAL
ADDRESS
Clock suspend mode is exited by registering CKE
The burst read/single write mode is entered by pro-
Clock Suspend During READ Burst
CLOCK
NOTE: For this example, CAS latency = 2, burst length = 4 or greater, and
CLK
CKE
DQ
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DQM is LOW.
T0
BANK,
READ
COL n
T1
NOP
Figure 23
T2
NOP
64Mb: x4, x8, x16
D
OUT
n
TRANSITIONING DATA
T3
n + 1
D
OUT
T4
NOP
©2003, Micron Technology, Inc.
SDRAM
T5
NOP
n + 2
D
OUT
DON’T CARE
T6
NOP
D
n + 3
OUT