mt48lc16m4a2tg Micron Semiconductor Products, mt48lc16m4a2tg Datasheet - Page 15

• Manufacturer Part Number: mt48lc16m4a2tg
• Description: 64mb X4, X8, X16 Sdram
• Manufacturer: Micron Semiconductor Products

READs
as shown in Figure 5.
vided with the READ command, and auto precharge is
either enabled or disabled for that burst access. If auto
precharge is enabled, the row being accessed is
precharged at the completion of the burst. For the ge-
neric READ commands used in the following illustra-
tions, auto precharge is disabled.
from the starting column address will be available fol-
lowing the CAS latency after the READ command. Each
subsequent data-out element will be valid by the next
positive clock edge. Figure 6 shows general timing for
each possible CAS latency setting.
64Mb: x4, x8, x16 SDRAM
64MSDRAM_F.p65 – Rev. F; Pub. 1/03
A8, A9, A11: x16
READ bursts are initiated with a READ command,
The starting column and bank addresses are pro-
During READ bursts, the valid data-out element
A9, A11: x8
A0-A9: x4
A0-A8: x8
A0-A7: x16
A11: x4
BA0,1
CAS#
RAS#
WE#
A10
CKE
CLK
CS#
READ Command
HIGH
Figure 5
DISABLE AUTO PRECHARGE
ENABLE AUTO PRECHARGE
ADDRESS
ADDRESS
COLUMN
BANK
15
mands have been initiated, the DQs will go High-Z. A
full-page burst will continue until terminated. (At the
end of the page, it will wrap to column 0 and continue.)
subsequent READ command, and data from a fixed-
length READ burst may be immediately followed by
data from a READ command. In either case, a continu-
ous flow of data can be maintained. The first data ele-
ment from the new burst follows either the last ele-
ment of a completed burst or the last desired data ele-
ment of a longer burst which is being truncated.
The new READ command should be issued x cycles
COMMAND
COMMAND
Upon completion of a burst, assuming no other com-
Data from any READ burst may be truncated with a
CLK
CLK
DQ
DQ
Micron Technology, Inc., reserves the right to change products or specifications without notice.
READ
READ
T0
T0
CAS Latency = 2
CAS Latency
Figure 6
NOP
NOP
T1
T1
t
t AC
LZ
CAS Latency = 3
64Mb: x4, x8, x16
T2
NOP
T2
NOP
t
t AC
LZ
D
t OH
OUT
©2003, Micron Technology, Inc.
SDRAM
T3
T3
NOP
D
t OH
OUT
DON’T CARE
UNDEFINED
T4