mt48lc16m4a2tg Micron Semiconductor Products, mt48lc16m4a2tg Datasheet - Page 22

• Manufacturer Part Number: mt48lc16m4a2tg
• Description: 64mb X4, X8, X16 Sdram
• Manufacturer: Micron Semiconductor Products

subsequent READ command, and data for a fixed-
length WRITE burst may be immediately followed by a
subsequent READ command. Once the READ com-
mand is registered, the data inputs will be ignored, and
WRITEs will not be executed. An example is shown in
Figure 17. Data n + 1 is either the last of a burst of two or
the last desired of a longer burst.
lowed by, or truncated with, a PRECHARGE command
to the same bank (provided that auto precharge was
not activated), and a full-page WRITE burst may be
truncated with a PRECHARGE command to the same
bank. The PRECHARGE command should be issued
64Mb: x4, x8, x16 SDRAM
64MSDRAM_F.p65 – Rev. F; Pub. 1/03
COMMAND
ADDRESS
Data for any WRITE burst may be truncated with a
Data for a fixed-length WRITE burst may be fol-
CLK
DQ
COMMAND
ADDRESS
WRITE
BANK,
COL n
CLK
D
T0
Random WRITE Cycles
DQ
n
IN
WRITE to READ
BANK,
WRITE
COL n
n + 1
D
T0
NOP
D
T1
n
IN
IN
TRANSITIONING DATA
TRANSITIONING DATA
Figure 16
Figure 17
WRITE
BANK,
COL a
BANK,
READ
COL b
T1
D
T2
a
IN
BANK,
WRITE
COL x
T2
D
T3
NOP
x
IN
WRITE
COL m
BANK,
T3
NOP
D
D
T4
m
IN
OUT
b
DON’T CARE
DON’T CARE
NOP
T5
b + 1
D
OUT
22
t
data element is registered. The auto precharge mode
requires a
of frequency. In addition, when truncating a WRITE
burst, the DQM signal must be used to mask input data
for the clock edge prior to, and the clock edge coinci-
dent with, the PRECHARGE command. An example is
shown in Figure 18. Data n + 1 is either the last of a burst
of two or the last desired of a longer burst. Following the
PRECHARGE command, a subsequent command to
the same bank cannot be issued until
completion, a PRECHARGE command issued at the
optimum time (as described above) provides the same
operation that would result from the same fixed-length
burst with auto precharge. The disadvantage of the
PRECHARGE command is that it requires that the com-
mand and address buses be available at the appropri-
ate time to issue the command; the advantage of the
PRECHARGE command is that it can be used to trun-
cate fixed-length or full-page bursts.
COMMAND
COMMAND
t WR @ t CLK 15ns
t WR = t CLK < 15ns
WR after the clock edge at which the last desired input
NOTE: DQM could remain LOW in this example if the WRITE burst is a fixed length of two.
ADDRESS
ADDRESS
In the case of a fixed-length burst being executed to
DQM
DQM
CLK
DQ
DQ
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BANK a,
BANK a,
t
WRITE
WRITE
COL n
COL n
D
D
WR of at least one clock plus time, regardless
T0
n
n
IN
IN
WRITE to PRECHARGE
n + 1
n + 1
NOP
NOP
T1
D
D
IN
IN
t
Figure 18
WR
PRECHARGE
(a or all)
BANK
NOP
T2
64Mb: x4, x8, x16
t
TRANSITIONING DATA
WR
PRECHARGE
(a or all)
BANK
T3
NOP
t RP
NOP
NOP
T4
t
RP is met.
t RP
©2003, Micron Technology, Inc.
SDRAM
BANK a,
ACTIVE
ROW
NOP
T5
DON’T CARE
BANK a,
ACTIVE
ROW
T6
NOP