mt48lc16m4a2tg Micron Semiconductor Products, mt48lc16m4a2tg Datasheet - Page 30

• Manufacturer Part Number: mt48lc16m4a2tg
• Description: 64mb X4, X8, X16 Sdram
• Manufacturer: Micron Semiconductor Products

TRUTH TABLE 4 – CURRENT STATE BANK n, COMMAND TO BANK m
(Notes: 1-6; notes appear below and on next page)
NOTE: 1. This table applies when CKE
64Mb: x4, x8, x16 SDRAM
64MSDRAM_F.p65 – Rev. F; Pub. 1/03
CURRENT STATE CS# RAS# CAS# WE#
Precharging
(With Auto
(With Auto
Activating,
Precharge)
Precharge)
Precharge
Precharge
Disabled)
Disabled)
Active, or
(Auto
(Auto
Write
Write
Read
Read
Row
Any
Idle
2. This table describes alternate bank operation, except where noted; i.e., the current state is for bank n and the
3. Current state definitions:
previous state was self refresh).
commands shown are those allowed to be issued to bank m (assuming that bank m is in such a state that the given
command is allowable). Exceptions are covered in the notes below.
Precharge Enabled: Starts with registration of a READ command with auto precharge enabled, and ends when
Precharge Enabled: Starts with registration of a WRITE command with auto precharge enabled, and ends when
H
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
Write w/Auto
Read w/Auto
Row Active: A row in the bank has been activated, and
H
H
H
H
H
H
X
X
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet
Read: A READ burst has been initiated, with auto precharge disabled, and has not yet terminated
Idle: The bank has been precharged, and
X
H
X
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
n-1
no register accesses are in progress.
or been terminated.
terminated or been terminated.
t
t
RP has been met. Once
RP has been met. Once
was HIGH and CKE
H
H
H
H
H
X
X
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
COMMAND (ACTION)
COMMAND INHIBIT (NOP/Continue previous operation)
WRITE (Select column and start WRITE burst)
PRECHARGE
PRECHARGE
NO OPERATION (NOP/Continue previous operation)
Any Command Otherwise Allowed to Bank m
ACTIVE (Select and activate row)
READ (Select column and start READ burst)
PRECHARGE
ACTIVE (Select and activate row)
READ (Select column and start new READ burst)
WRITE (Select column and start WRITE burst)
ACTIVE (Select and activate row)
READ (Select column and start READ burst)
WRITE (Select column and start new WRITE burst)
ACTIVE (Select and activate row)
READ (Select column and start new READ burst)
WRITE (Select column and start WRITE burst)
PRECHARGE
ACTIVE (Select and activate row)
READ (Select column and start READ burst)
WRITE (Select column and start new WRITE burst)
PRECHARGE
(Continued on next page)
n
is HIGH (see Truth Table 2) and after
30
t
t
RP is met, the bank will be in the idle state.
RP is met, the bank will be in the idle state.
t
RP has been met.
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
RCD has been met. No data bursts/accesses and
64Mb: x4, x8, x16
t
XSR has been met (if the
©2003, Micron Technology, Inc.
SDRAM
NOTES
7, 8, 14
7, 8, 15
7, 8, 16
7, 8, 17
7, 10
7, 11
7, 12
7, 13
7
7
9
9
9
9