mc68hc908jb16 Freescale Semiconductor, Inc, mc68hc908jb16 Datasheet - Page 117

• Manufacturer Part Number: mc68hc908jb16
• Description: M68hc08 Microcontrollers Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

MC68HC908JB16
Freescale Semiconductor
INT/BREAK
OSCDCLK
IAB
NOTE:
NOTE:
—
Figure 8-18. Stop Mode Recovery from Interrupt or Break
Rev. 1.1
The SIM disables the oscillator signals (OSCOUT and OSCDCLK) in
stop mode, stopping the CPU and peripherals. Stop recovery time is
selectable using the SSREC bit in the configuration register (CONFIG).
If SSREC is set, stop recovery is reduced from the normal delay of 4096
OSCDCLK cycles down to 2048. This is ideal for applications using
canned oscillators that do not require long startup times from stop mode.
External crystal applications should use the full stop recovery time by
clearing the SSREC bit.
A break interrupt during stop mode sets the SIM break stop/wait bit
(SBSW) in the SIM break status register (SBSR).
The SIM counter is held in reset from the execution of the STOP
instruction until the beginning of stop recovery. It is then used to time the
recovery period.
To minimize stop current, all pins configured as inputs should be driven
to a logic 1 or logic 0.
CPUSTOP
NOTE: Previous data can be operand data or the STOP opcode, depending on the last instruction
STOP +1
R/W
IDB
IAB
System Integration Module (SIM)
STOP ADDR
Figure 8-17. Stop Mode Entry Timing
Figure 8-17
STOP + 2
PREVIOUS DATA
STOP RECOVERY PERIOD
STOP + 2
STOP ADDR + 1
shows stop mode entry timing.
NEXT OPCODE
SP
System Integration Module (SIM)
SAME
SP – 1
SAME
SP – 2
SAME
Technical Data
SP – 3
SAME
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