mc68hc908jb16 Freescale Semiconductor, Inc, mc68hc908jb16 Datasheet - Page 319

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mc68hc908jb16

Manufacturer Part Number
mc68hc908jb16
Description
M68hc08 Microcontrollers Microcontroller
Manufacturer
Freescale Semiconductor, Inc
Datasheet

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20.7 Control Timing
20.8 Oscillator Characteristics
MC68HC908JB16
Freescale Semiconductor
Notes:
Notes:
Notes:
Internal operating frequency
RST input pulse width low
Crystal frequency
External clock
Reference frequency
Crystal load capacitance
Crystal fixed capacitance
Crystal tuning capacitance
Feedback bias resistor
Series resistor
1. V
2. Typical values reflect average measurements at midpoint of voltage range, 25 °C only.
3. Run (operating) I
4. Wait I
5. STOP I
6. Maximum is highest voltage that POR is guaranteed.
7. If minimum V
1. V
2. Some modules may require a minimum frequency greater than dc for proper operation; see appropriate table for this
3. Minimum pulse width reset is guaranteed to be recognized. It is possible for a smaller pulse width to cause a reset.
1. The USB module is designed to operate with f
2. No more than 10% duty cycle deviation from 50%.
3. Consult crystal vendor data sheet.
4. Not required for high-frequency crystals.
loads. Less than 100 pF on all outputs. C
affects run I
than 100 pF on all outputs. C
as inputs; OSC2 capacitance linearly affects wait I
V
information.
DD
DD
DD
= 4.0 to 5.5 Vdc, V
= 4.0 to 5.5 Vdc; V
is reached.
DD
DD
measured using external square wave clock source (f
Characteristic
measured with USB in suspend mode; OSC1 grounded; no port pins sourcing current.
DD
DD
(3), (4)
. Measured with all modules enabled.
is not reached before the internal POR reset is released, RST must be driven low externally until minimum
DD
(1)
Rev. 1.1
measured using external square wave clock source (f
(1), (2)
Characteristic
SS
SS
(3)
(3)
(3)
= 0 Vdc, T
= 0 Vdc; timing shown with respect to 20% V
(3)
(2)
L
= 20 pF on OSC2; 15 kΩ ± 5% termination resistors on D+ and D– pins; all ports configured
A
= T
(1)
L
L
to T
= 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly
Symbol
Electrical Specifications
XCLK
f
f
XCLK
XCLK
H
C
C
C
R
R
, unless otherwise noted.
B
S
L
1
2
DD
= 12 MHz.
Min
XCLK
dc
1
= 12MHz); all inputs 0.2 V from rail; no dc loads; less
Symbol
DD
t
f
IRL
OP
XCLK
and 70% V
10 MΩ
2 × C
2 × C
Typ
12
12
= 12MHz). All inputs 0.2 V from rail. No dc
L
L
DD
Min
125
, unless otherwise noted.
Max
12
12
Electrical Specifications
Max
6
Technical Data
MHz
MHz
Unit
MHz
Unit
ns
319

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