mc68hc908jb16 Freescale Semiconductor, Inc, mc68hc908jb16 Datasheet - Page 255

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mc68hc908jb16

Manufacturer Part Number
mc68hc908jb16
Description
M68hc08 Microcontrollers Microcontroller
Manufacturer
Freescale Semiconductor, Inc
Datasheet

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13.8 Programming the PLL
13.9 CGM I/O Registers
MC68HC908JB16
Freescale Semiconductor
NOTE:
Rev. 1.1
With the PLLs off (PLLON = 0), use the following procedure to initialize
both PLLs:
Then for each PLL, use the following procedure to program the VCO and
reference dividers:
To reprogram the PLL frequency, clear the PLLON bit (PLLON =0) and
repeat steps 3 to 6.
Do not program both PLLs to the same frequency. A difference of 50kHz
or more is recommended between the two PLL outputs.
These registers control and monitor operation of the CGMs:
1. Write $80 to the VCO control register (PVCR).
2. Write $70 to the phase detector register (PDCR).
3. Write data to the VCO and reference divider select register high
4. Write data to the VCO divider select register low (PNSL).
5. Write data to the reference divider select register low (PRSL).
6. Set PLLON = 1 in the bandwidth control register to enable the PLL.
(PNRH).
Bandwidth control register (PBWC)
VCO control register (PVCR)
PLL1 VCO and reference divider select register high (PNRH1)
PLL1 VCO divider select register low (PNSL1)
PLL1 reference divider select register low (PRSL1)
PLL2 VCO and reference divider select register high (PNRH2)
PLL2 VCO divider select register low (PNSL2)
PLL2 reference divider select register low (PRSL2)
Phase detector control register (PDCR)
Clock Generator Module (CGM)
Clock Generator Module (CGM)
Technical Data
255

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