mc68hc05pv8a Freescale Semiconductor, Inc, mc68hc05pv8a Datasheet - Page 121

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mc68hc05pv8a

Manufacturer Part Number
mc68hc05pv8a
Description
Mc68hc05pv8a Microcontroller
Manufacturer
Freescale Semiconductor, Inc
Datasheet
8.3.2 Computer Operating Properly (COP) Watchdog Reset
8.3.3 Core Timer Counter Register (CTCR)
MC68HC(8)05PV8/A — Rev. 1.9
RT1:RT0
00
01
10
11
1835.000ms
229.376ms
458.752ms
917.504ms
500 kHz
The COP watchdog timer function is implemented on this device by
using the output of the RTI circuit and further dividing it by eight. The
minimum COP reset rates are listed in
out, an internal reset is generated and the normal reset vector is fetched.
A COP time-out is prevented by clearing bit 0 of address $3FF0. When
the COP is cleared, only the final divide by eight stage (output of the RTI)
is cleared.
The timer counter register is a read-only register which contains the
current value of the 8-bit ripple counter at the beginning of the timer
chain. This counter is clocked at f
various functions including a software input capture. Extended time
periods can be attained using the TOF function to increment a temporary
RAM storage location thereby simulating a 16-bit (or more) counter.
Reset:
$0009
Read:
Write:
Freescale Semiconductor, Inc.
Table 8-2 Minimum COP Reset Times
Minimum COP Reset Bus Frequency at f
For More Information On This Product,
Bit 7
bit 7
Figure 8-3 Core Timer Counter Register (CTCR)
0
1.000 MHz
114.689ms
229.376ms
458.752ms
917.504ms
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bit 6
6
0
Core Timer
2.000 MHz
114.689ms
229.376ms
458.752ms
57.344ms
bit 5
5
0
bit 4
op
4
0
divided by 4 and can be used for
2.4576 MHz
Table
186.666ms
373.333ms
46.666ms
93.333ms
OP
bit 3
3
0
specified:
8-2. If the COP circuit times
bit 2
2
0
7*2
7*2
7*2
7*2
RATIO
14
15
16
17
/f
/f
/f
/f
op
op
op
op
bit 1
1
0
Technical Data
Core Timer
Registers
Bit 0
bit 0
0

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