mc68hc05pv8a Freescale Semiconductor, Inc, mc68hc05pv8a Datasheet - Page 156

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mc68hc05pv8a

Manufacturer Part Number
mc68hc05pv8a
Description
Mc68hc05pv8a Microcontroller
Manufacturer
Freescale Semiconductor, Inc
Datasheet
Technical Data
12.5 Trimming the Voltage Regulator
Technical Data
Any loss of V
reset. The device remains in the reset state for the duration of the LVR
condition or until the internal V
device, at which point reset no longer has meaning. If the drop in V
that triggers an LVR is transient, then an internal RST is asserted for a
minimum 4064 cycles of the CPU bus clock, PH2 (the POR delay).
On the MC68HC05PV8A, the low voltage reset is generated by a second
low voltage reset generator with a lower threshold as long as the ULPM
bit is set. For this reason, it is mendatory to have the ULPM bit cleared
as long as the mcu is in normal operation.
The output of the voltage regulator can be trimmed to reach a higher
accuracy. This is performed by setting the VT2, VT1 and VT0 bits in the
MFTEST register
Table 12-1
decrease of the output voltage by trimming steps (typically 40mV).
$002F
Reset:
Read:
Write:
Freescale Semiconductor, Inc.
For More Information On This Product,
HVTOFF
Bit 7
0
illustrates the effect of the trimming bits to V
Figure 12-1 MFTEST Register (MFTEST)
DD
Go to: www.freescale.com
Voltage Regulator
sufficient to trigger an LVR causes the device to be
6
0
0
Table 12-1 Trimming Effect
VT2
0
0
0
0
1
1
1
1
5
0
0
VT1
DD
0
0
1
1
0
0
1
1
VSCAL
drops below the functional level of the
4
0
VT0
0
1
0
1
0
1
0
1
LSOFF
3
0
MC68HC(8)05PV8/A — Rev. 1.9
Effect
–1
–2
–3
+4
+3
+2
+1
0
VT2
2
0
DD
in increase or
VT1
1
0
Bit 0
VT0
0
DD

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