mc68hc05pv8a Freescale Semiconductor, Inc, mc68hc05pv8a Datasheet - Page 70

• Manufacturer Part Number: mc68hc05pv8a
• Description: Mc68hc05pv8a Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

Technical Data
4.4 Reset Interrupt Sequence
4.5 Software Interrupt (SWI)
4.6 Hardware Interrupts
4.7 External Interrupt (IRQ)
Technical Data
The reset function is not in the strictest sense an interrupt; however, it is
acted upon in a similar manner as shown in
on the RESET pin or internally generated RST signal causes the
program to vector to its starting address which is specified by the
contents of memory locations $3FFE and $3FFF. The I-bit in the
condition code register is also set. The MCU is configured to a known
state during this type of reset as described in
The SWI is an executable instruction and a non-maskable interrupt since
it is executed regardless of the state of the I-bit in the CCR. If the I-bit is
zero (interrupts enabled), the SWI instruction executes after interrupts
which were pending before the SWI was fetched, or before interrupts
generated after the SWI was fetched. The interrupt service routine
address is specified by the contents of memory locations $3FFC and
$3FFD.
All hardware interrupts except RESET are maskable by the I-bit in the
CCR. If the I-bit is set, all hardware interrupts (internal and external) are
disabled. Clearing the I-bit enables the hardware interrupts. There are
two types of hardware interrupts which are explained in the following
sections.
If the interrupt mask bit (I-bit) of the CCR has been cleared and the
interrupt enable bit is set (INTE bit) and the signal of the external
interrupt pin (IRQ) satisfies the condition selected by the option control
bits (INTP and INTN), then the external interrupt is recognized. INTE,
INTP and INTN are all bits contained in the system control register
located at $000A. When the interrupt is recognized, the current state of
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Interrupts
Figure
MC68HC(8)05PV8/A — Rev. 1.9
Section 5.
4-1. A low level input
Resets.