mc68hc705e5 Freescale Semiconductor, Inc, mc68hc705e5 Datasheet - Page 100

• Manufacturer Part Number: mc68hc705e5
• Description: M68hc05 Family Of Microcontrollers Mcus
• Manufacturer: Freescale Semiconductor, Inc

Synchronous Serial Interface (SSI)
12.4 SSI Registers
12.4.1 SSI Control Register
General Release Specification
Address:
The SSI registers are described in the following subsections.
This register is located at address $000A. A reset clears all of these bits,
except bit 3 which is set. Writes to this register during a transfer should
be avoided, with the exception of clearing the SE bit to disable the SSI.
In addition, the clock polarity, rate, data format, and master/slave
selection should not be changed while the SSI is enabled (SE = 1) or
being enabled. Always disable the SSI, by clearing the SE bit, before
altering control bits within the SCR.
SIE — SSI Interrupt Enable
SE — SSI Enable
Reset:
Read:
Write:
This bit determines whether an interrupt request should be generated
when a transfer is complete. Reset clears this bit.
When this bit is set, it enables the SSI and SCK pins. When this bit is
cleared, any transmission in progress is aborted and the SCK and
SDIO are three-stated. The SE bit is readable and writable any time.
Clearing SE while a data transfer is occurring will abort the
transmission and reset the bit counter. Reset clears this bit.
Freescale Semiconductor, Inc.
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1 = An interrupt request will be made if the CPU is in the run or wait
0 = No interrupt requests will be made by the SSI.
1 = Enable the SSI module.
0 = Disable the SSI module.
$000A
Bit 7
SIE
Synchronous Serial Interface (SSI)
mode of operation and the status flag bit SF is set.
0
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Figure 12-4. SSI Control Register (SCR)
SE
6
0
LSBF
5
0
MSTR
4
0
CPOL
3
1
MC68HC705E5
SDIR
2
0
SR1
1
0
—
Rev. 1.0
Bit 0
SR0
0