mc68hc705e5 Freescale Semiconductor, Inc, mc68hc705e5 Datasheet - Page 98

• Manufacturer Part Number: mc68hc705e5
• Description: M68hc05 Family Of Microcontrollers Mcus
• Manufacturer: Freescale Semiconductor, Inc

Synchronous Serial Interface (SSI)
12.3 SSI Signals
12.3.1 Serial Clock (SCK)
12.3.2 Serial Data Input/Output (SDIO)
General Release Specification
NOTE:
The following sections describe the SSI signals.
In master mode (MSTR = 1), the SCK pin is an output with a selectable
frequency of:
This pin will be high (CPOL = 1) or low (CPOL = 0) between
transmissions.
In slave mode (MSTR = 0), the SCK pin is an input and the clock must
be supplied by an external master with a maximum frequency of f
divided by 2. There is no minimum SCK frequency. This pin should be
driven high (CPOL = 1) or low (CPOL = 0) between transmissions by the
external master and must be stable before the SSI is first enabled
(SE = 1).
Data is always captured with the SDIO pin on the rising edge of SCK.
Data is always shifted out and presented at the SDIO pin on the falling
edge of SCK.
This pin receives and transmits data to or from the SSI module as
described in the following paragraphs.
SDIO as an Output Pin
f
f
f
f
Prior to enabling the SSI (SE = 0), the SDIO pin will be three-stated.
The SDIO pin will be active when the SSI is enabled (SE = 1), the
serial direction (SDIR = 1) bit is set, and MSTR = 1. The state of the
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divided by 8 (SR1:SR0 = 01),
divided by 16 (SR1:SR0 = 00),
divided by 4 (SR1:SR0 = 10), or
divided by 2 (SR1:SR0 = 11).
Synchronous Serial Interface (SSI)
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MC68HC705E5
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Rev. 1.0
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