mc68hc705e5 Freescale Semiconductor, Inc, mc68hc705e5 Datasheet - Page 69

• Manufacturer Part Number: mc68hc705e5
• Description: M68hc05 Family Of Microcontrollers Mcus
• Manufacturer: Freescale Semiconductor, Inc

MC68HC705E5
NOTE:
NOTE:
—
Rev. 1.0
COPR — COP Reset
The COP watchdog reset is a mask option. Therefore, a COP reset will
only occur when this option is enabled. This option cannot be disabled
by software.
CRS1 and CRS0 — COP Rate Select
Although these bits default to zero, the user should write to these bits to
prevent subsequent writes from changing the COP rate.
A bit set/clear for any bit in this register is executed as a
read-modify-write of this register. If used as the first write to this register,
further writes to CRS1 and CRS0 would not be valid, and the default
value would be set.
COPR is a read-only status bit. This bit is set by a COP reset, but is
cleared by POR, external reset, or illegal address reset.
The value of these two bits determines the COP timeout rate. These
bits can be written only on the first write to this register after reset. If
these bits are never written to, the COP reset rate will be set at one
second. The COP counter chain is cleared when these bits are
written.
Freescale Semiconductor, Inc.
Computer Operating Properly (COP) Watchdog
For More Information On This Product,
1 = Last reset was a COP reset.
0 = Last reset was not a COP reset.
CRS1
Go to: www.freescale.com
Table 10-1. COP Rates at f
0
0
1
1
CRS0
0
1
0
1
Computer Operating Properly (COP) Watchdog
Minimum COP Rate
osc
System Control and Status Register
2 seconds
4 seconds
8 seconds
1 second
= 32.768 kHz
General Release Specification