mc68hc705e5 Freescale Semiconductor, Inc, mc68hc705e5 Datasheet - Page 63

• Manufacturer Part Number: mc68hc705e5
• Description: M68hc05 Family Of Microcontrollers Mcus
• Manufacturer: Freescale Semiconductor, Inc

9.3 Phase-Locked Loop Control Register
MC68HC705E5
—
Rev. 1.0
Address:
This read/write register contains the control bits which select the PLL
frequency and enable/disable the synthesizer.
BCS — Bus Clock Select
BWC — Bandwidth Control
Reset:
Read:
Write:
When this bit is set, the output of the PLL is used to generate the
internal processor clock. When clear, the internal bus clock is driven
by the crystal (OSC1
up to 1.5 OSC1 cycles + 1.5 PLLOUT cycles to make the transition.
During the transition, the clock select output will be held low and all
CPU and timer activity will cease until the transition is complete.
Before setting BCS, allow at least a time of t
This bit cannot be set unless the PLLON bit is already set on a
previous instruction. Reset clears this bit.
This bit selects high bandwidth control when set and low bandwidth
control when clear. The low bandwidth driver is always enabled, so
this bit determines whether the high bandwidth driver is on or off.
When the PLL is turned on, the BWC bit should be set to a logic 1 for
a time of 90% t
to the desired frequency. The BWC bit should then be cleared and
software should delay for a time 10% t
make the final adjustments. The PLL clock cannot be used (BCS bit
set). Although it is NOT prohibited in hardware, the BCS bit should not
be set unless the BWC bit is cleared and the proper delay times have
been followed. The PLL will generate a lower jitter clock when the
BWC bit is cleared. Reset clears this bit.
Freescale Semiconductor, Inc.
Figure 9-2. Phase-Locked Loop Control Register (PLLCR)
For More Information On This Product,
$0007
Phase-Locked Loop (PLL) Synthesis
Bit 7
0
0
Go to: www.freescale.com
BCS
PLLS
6
0
to allow the PLL time to acquire a frequency close
2). Once BCS has been changed, it may take
5
0
0
BWC
4
0
PLLON
Phase-Locked Loop Control Register
Phase-Locked Loop (PLL) Synthesis
PLLS
3
1
General Release Specification
to allow the PLL time to
PLLS
VCOTST
2
1
after PLLON is set.
PS1
1
0
Bit 0
PS0
1