mc68hc705e5 Freescale Semiconductor, Inc, mc68hc705e5 Datasheet - Page 84

• Manufacturer Part Number: mc68hc705e5
• Description: M68hc05 Family Of Microcontrollers Mcus
• Manufacturer: Freescale Semiconductor, Inc

Motorola Bus (M Bus) Interface
11.6.4 M-Bus Status Register
General Release Specification
Address:
This status register is software readable only with exception of bit 1
(MIF) and bit 4 (MAL) which are software clearable. All bits are cleared
upon reset except bit 7 (MCF) and bit 0 (RXAK).
MCF — Data Transferring Bit
MAAS — Addressed as a Slave Bit
MBB — Bus Busy Bit
Reset:
Read:
Write:
While one byte of data is being transferred, this bit is cleared. It is set
by the falling edge of the ninth clock of a byte transfer.
When its own specific address (MADR) is matched with the calling
address, this bit is set. The CPU is interrupted provided MIEN is set.
Then CPU needs to check the SRW bit and set its TX/RX mode
accordingly.
Writing to the M-bus control register clears this bit.
This bit indicates the status of the bus. When a start signal is
detected, the MBB is set. If a stop signal is detected, it is cleared.
Freescale Semiconductor, Inc.
For More Information On This Product,
1 = Transfer complete
0 = Transfer in progress
1 = Addressed as a slave
0 = Not addressed
1 = Bus busy
0 = Bus idle
$001B
MCF
Bit 7
1
Motorola Bus (M Bus) Interface
Figure 11-7. M-Bus Status Register (MSR)
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= Unimplemented
MAAS
6
0
MBB
5
0
MAL CLR
MAL
4
0
—
3
MC68HC705E5
SRW
2
0
MIF CLR
MIF
1
0
—
Rev. 1.0
RXAK
Bit 0
1