mc68hc705e5 Freescale Semiconductor, Inc, mc68hc705e5 Datasheet - Page 82

• Manufacturer Part Number: mc68hc705e5
• Description: M68hc05 Family Of Microcontrollers Mcus
• Manufacturer: Freescale Semiconductor, Inc

Motorola Bus (M Bus) Interface
11.6.3 M-Bus Control Register
General Release Specification
Address:
The M-bus control register (MCR) provides five control bits and is
cleared upon reset.
MEN — M-Bus Enable Bit
MIEN — M-Bus Interrupt Enable Bit
MSTA — Master/Slave Mode Select Bit
Reset:
Read:
Write:
If MEN is set, the M-bus interface system is enabled. If MEN is
cleared, the interface is reset and disabled. The MEN bit must be set
first before any bits of MCR are set.
If MIEN is set, an interrupt occurs provided the MIF flag in the status
register is set and the I bit in the condition code register is cleared. If
MIEN is cleared, the M-bus interrupt is disabled.
Upon reset, this bit is cleared. When this bit is changed from a logic 0
to a logic 1, a start signal is generated on the bus, and master mode
is selected. When this bit is changed from a logic 1 to a logic 0, a stop
signal is generated and the operating mode changes from master to
slave.
In master mode, a bit clear immediately followed by a bit set
generates a repeated start signal (see
generating a stop signal.
Freescale Semiconductor, Inc.
For More Information On This Product,
1 = Master
0 = Slave
$001A
MEN
Bit 7
0
Motorola Bus (M Bus) Interface
Figure 11-6. M-Bus Control Register (MCR)
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= Unimplemented
MIEN
6
0
MSTA
5
0
MTX
4
0
TXAK
Figure
3
0
MMUX
MC68HC705E5
11-1) without
2
0
—
1
—
Rev. 1.0
Bit 0
—