mc68hc705e5 Freescale Semiconductor, Inc, mc68hc705e5 Datasheet - Page 39

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mc68hc705e5

Manufacturer Part Number
mc68hc705e5
Description
M68hc05 Family Of Microcontrollers Mcus
Manufacturer
Freescale Semiconductor, Inc
Datasheet
4.7 Custom Periodic Interrupt (CPI)
MC68HC705E5
Rev. 1.0
Address
The CPI flag and enable bits are located in the CPI control and status
register (CPICSR). A CPI interrupt will vector to the interrupt service
routine located at the address specified by the contents of memory
location $1FF6 and $1FF7.
The custom periodic interrupt is mask programmable to a 0.25 second,
0.5 second, or 1 second interrupt. The interrupt is generated from the
32-kHz OSC1 input by a 15-bit counter. This interrupt is under the
control of the custom periodic interrupt control and status register
located at $12.
CPIF — Custom Periodic Interrupt Flag
CPIE — Custom Periodic Interrupt Enable
Reset:
Read:
Write:
CPIF is a clearable, read-only status bit and is set when the 15-bit
counter changes from $7FFF to $0000. A CPU interrupt request will
be generated if CPIE is set. Clearing the CPIF is done by writing a
zero to it. Writing a one to CPIF has no effect on the bit’s value. Reset
clears CPIF.
When this bit is cleared, the CPI interrupts are disabled. When this bit
is set, the CPU interrupt request is generated when the CPIF bit is set.
Reset clears this bit.
Freescale Semiconductor, Inc.
For More Information On This Product,
$0012
Bit 7
0
0
Figure 4-3. Custom Periodic Interrupt Control
Go to: www.freescale.com
CPIF
6
0
and Status Register (CPICSR)
Interrupts
5
0
0
CPIE
4
0
3
0
0
Custom Periodic Interrupt (CPI)
General Release Specification
2
0
0
1
0
0
Interrupts
Bit 0
0
0

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