mc68hc705e5 Freescale Semiconductor, Inc, mc68hc705e5 Datasheet - Page 62

• Manufacturer Part Number: mc68hc705e5
• Description: M68hc05 Family Of Microcontrollers Mcus
• Manufacturer: Freescale Semiconductor, Inc

Phase-Locked Loop (PLL) Synthesis
General Release Specification
OSCILLATOR
CRYSTAL
OSC1
t
REF
DETECT
PHASE
t
FB
To change PLL frequencies, follow the procedure outlined here:
The user cannot switch among the high speeds with the BCS bit set.
Following the procedure above will prevent possible bursts of
high-frequency operation during the re-configuration of the PLL.
Whenever the PLL is first enabled, the wide bandwidth mode should be
used. This enables the PLL frequency to ramp up quickly. When the
output frequency is near the desired frequency, the filter is switched to
the narrow bandwidth mode to make the final frequency more stable.
PCOMP
1. Clear BCS to enable the low-frequency bus rate.
2. Clear PLLON to disable the PLL and select high bandwidth.
3. Select the speed using PS1 and PS0.
4. Set PLLON to enable the PLL.
5. Wait a time of 90% t
6. Set BCS to switch to the high-frequency bus rate
0.1 F
Freescale Semiconductor, Inc.
For More Information On This Product,
select manual low bandwidth, wait another 10% t
Phase-Locked Loop (PLL) Synthesis
Figure 9-1. PLL Circuit
Go to: www.freescale.com
LOOP FILTER
FREQUENCY
PS1
DIVIDER
V
DDSYN
0.1 F
PS0
XFC
PLLS
VCO
for the PLL frequency to stabilize and
PLLOUT
SELECT
CLOCK
BCS
MC68HC705E5
OSC1
PLLS
2
.
—
GENERATION
CIRCUITRY
TO CLOCK
Rev. 1.0