mc68hc705e5 Freescale Semiconductor, Inc, mc68hc705e5 Datasheet - Page 34

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mc68hc705e5

Manufacturer Part Number
mc68hc705e5
Description
M68hc05 Family Of Microcontrollers Mcus
Manufacturer
Freescale Semiconductor, Inc
Datasheet
Interrupts
General Release Specification
Unlike RESET, hardware interrupts do not cause the current instruction
execution to be halted, but are considered pending until the current
instruction is complete. The current instruction is the one already fetched
and being operated on.
When the current instruction is complete, the processor checks all
pending hardware interrupts. If interrupts are not masked (CCR I bit
clear) and the corresponding interrupt enable bit is set, the processor
proceeds with interrupt processing; otherwise, the next instruction is
fetched and executed.
If both an external interrupt and a timer interrupt are pending at the end
of an instruction execution, the external interrupt is serviced first. The
SWI is executed the same as any other instruction, regardless of the I-bit
state.
Register
CPICSR
TCSR
Freescale Semiconductor, Inc.
MSR
SSR
N/A
N/A
N/A
N/A
For More Information On This Product,
Table 4-1. Vector Address for Interrupts and Reset
Name
CPIF
RTIF
Flag
TOF
Go to: www.freescale.com
N/A
N/A
N/A
MIF
SF
Reset
Software
External Interrupt
Timer Overflow
Real-Time Interrupt
Custom Periodic Interrupt
Synchronous Serial Interrupt
M-Bus Interrupt
Interrupts
Interrupts
Interrupt
RESET
TIMER
TIMER
M Bus
CPU
MC68HC705E5
SWI
IRQ
CPI
SSI
$1FFC–$1FFD
$1FFE–$1FFF
$1FFA–$1FFB
$1FF8–$1FF9
$1FF8–$1FF9
$1FF6–$1FF7
$1FF4–$1FF5
$1FF2–$1FF3
Address
Vector
Rev. 1.0

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