W83977EF Winbond Electronics Corp America, W83977EF Datasheet - Page 3

• Manufacturer Part Number: W83977EF
• Description: Description = W83877TF Plus Kbc, GP I/O, Wake-Up, Power Fail Resume ;; Package = QFP 128
• Manufacturer: Winbond Electronics Corp America

GENERAL DESCRIPTION ..................................................................................................................... 1
FEATURES ............................................................................................................................................. 2
PIN CONFIGURATION ........................................................................................................................... 5
1.0 PIN DESCRIPTION.......................................................................................................................... 6
2.0 FDC FUNCTIONAL DESCRIPTION............................................................................................... 19
3.0 UART PORT.................................................................................................................................... 45
1.1 H
1.2 G
1.3 S
1.4 I
1.5 M
1.6 FDC I
1.7 KBC I
1.8 POWER PINS .............................................................................................................................. 18
1.9 ACPI I
2.1 W83977EF FDC .......................................................................................................................... 19
2.2 R
3.1 U
3.2 R
2.1.1 AT interface ........................................................................................................................... 19
2.1.2 FIFO (Data) ........................................................................................................................... 19
2.1.3 Data Separator...................................................................................................................... 20
2.1.4 Write Precompensation......................................................................................................... 20
2.1.5 Perpendicular Recording Mode ............................................................................................ 21
2.1.5 Perpendicular Recording Mode ............................................................................................ 21
2.1.6 FDC Core .............................................................................................................................. 21
2.1.7 FDC Commands ................................................................................................................... 21
2.2.1 Status Register A (SA Register) (Read base address + 0) .................................................. 33
2.2.2 Status Register B (SB Register) (Read base address + 1) .................................................. 35
2.2.3 Digital Output Register (DO Register) (Write base address + 2).......................................... 37
2.2.4 Tape Drive Register (TD Register) (Read base address + 3) .............................................. 37
2.2.5 Main Status Register (MS Register) (Read base address + 4) ............................................ 38
2.2.6 Data Rate Register (DR Register) (Write base address + 4) ............................................... 38
2.2.7 FIFO Register (R/W base address + 5) ................................................................................ 40
2.2.8 Digital Input Register (DI Register) (Read base address + 7) .............................................. 42
2.2.9 Configuration Control Register (CC Register) (Write base address + 7) ............................. 43
3.2.1 UART Control Register (UCR) (Read/Write) ........................................................................ 45
3.2.2 UART Status Register (USR) (Read/Write) .......................................................................... 48
3.2.3 Handshake Control Register (HCR) (Read/Write)................................................................ 48
NFRARED
ERIAL
OST
EGISTER
NIVERSAL
EGISTER
ENERAL
ULTI
I
-M
NTERFACE
NTERFACE
NTERFACE
NTERFACE
P
ODE
ORT
P
I
D
A
NTERFACE
URPOSE
A
DDRESS
ESCRIPTIONS
SYNCHRONOUS
P
I
NTERFACE
ARALLEL
............................................................................................................................ 16
............................................................................................................................ 18
............................................................................................................................. 6
........................................................................................................................... 18
I/O P
...................................................................................................................... 45
..................................................................................................................... 10
P
TABLE OF CONTENTS
.................................................................................................................. 9
............................................................................................................... 33
ORT
ORT
R
.......................................................................................................... 8
........................................................................................................ 11
ECEIVER
/T
RANSMITTER
-II -
(UART A, UART B) .................................... 45
Publication Release Date: April 2003
W83977EF
Revision 1.1