W83977EF Winbond Electronics Corp America, W83977EF Datasheet - Page 54

• Manufacturer Part Number: W83977EF
• Description: Description = W83877TF Plus Kbc, GP I/O, Wake-Up, Power Fail Resume ;; Package = QFP 128
• Manufacturer: Winbond Electronics Corp America

This 8-bit register provides information about the status of the data transfer during communication.
Bit 7: RFEI. In 16450 mode, this bit is always set to a logic 0. In 16550 mode, this bit is set to a logic 1
Bit 6: TSRE. In 16450 mode, when TBR and TSR are both empty, this bit will be set to a logical 1. In
Bit 5: TBRE. In 16450 mode, when a data character is transferred from TBR to TSR, this bit will be set
Bit 4: SBD. This bit is set to a logical 1 to indicate that received data are kept in silent state for a full
Bit 3: NSER. This bit is set to a logical 1 to indicate that the received data have no stop bit. In 16550
Bit 2: PBER. This bit is set to a logical 1 to indicate that the parity bit of received data is wrong. In
Bit 1: OER. This bit is set to a logical 1 to indicate received data have been overwritten by the next
Bit 0: RDR. This bit is set to a logical 1 to indicate received data are ready to be read by the CPU in
3.2.2 UART Status Register (USR) (Read/Write)
3.2.3 Handshake Control Register (HCR) (Read/Write)
when there is at least one parity bit error, no stop bit error or silent byte detected in the FIFO. In
16550 mode, this bit is cleared by reading from the USR if there are no remaining errors left in
the FIFO.
16550 mode, if the transmit FIFO and TSR are both empty, it will be set to a logical 1. Other
thanthese two cases, this bit will be reset to a logical 0.
to a logical 1. If ETREI of ICR is a logical 1, an interrupt will be generated to notify the CPU to
write the next data. In 16550 mode, this bit will be set to a logical 1 when the transmit FIFO is
empty. It will be reset to a logical 0 when the CPU writes data into TBR or FIFO.
word time, including start bit, data bits, parity bit, and stop bits. In 16550 mode, it indicates the
same condition for the data on top of the FIFO. When the CPU reads USR, it will clear this bit to
a logical 0.
mode, it indicates the same condition for the data on top of the FIFO. When the CPU reads
USR, it will clear this bit to a logical 0.
16550 mode, it indicates the same condition for the data on top of the FIFO. When the CPU
reads USR, it will clear this bit to a logical 0.
received data before they were read by the CPU. In 16550 mode, it indicates the same
condition instead of FIFO full. When the CPU reads USR, it will clear this bit to a logical 0.
the RBR or FIFO. After no data are left in the RBR or FIFO, the bit will be reset to a logical 0.
7
6
5
4
3
2
1
0
-48 -
Overrun error (OER)
Parity bit error (PBER)
No stop bit error (NSER)
Silent byte detected (SBD)
Transmitter Buffer Register empty (TBRE)
Transmitter Shift Register empty (TSRE)
RBR Data ready (RDR)
RX FIFO Error Indication (RFEI)
Publication Release Date: April 2003
W83977EF
Revision 1.1