W83977EF Winbond Electronics Corp America, W83977EF Datasheet - Page 70

• Manufacturer Part Number: W83977EF
• Description: Description = W83877TF Plus Kbc, GP I/O, Wake-Up, Power Fail Resume ;; Package = QFP 128
• Manufacturer: Winbond Electronics Corp America

This mode is defined only for the forward direction. The standard parallel port protocol is used by a
hardware handshake to the peripheral to transmit bytes written or DMAed from the system to this
FIFO. Transfers to the FIFO are byte aligned.
When the direction bit is 0, bytes written or DMAed from the system to this FIFO are transmitted by a
hardware handshake to the peripheral using the ECP parallel port protocol. Transfers to the FIFO are
byte aligned.
When the direction bit is 1, data bytes from the peripheral are read under automatic hardware
handshake from ECP into this FIFO. Reads or DMAs from the FIFO will return bytes of ECP data to
the system.
Data bytes may be read, written, or DMAed to or from the system to this FIFO in any direction. Data in
the tFIFO will not be transmitted to the parallel port lines. However, data in the tFIFO may be
displayed on the parallel port data lines.
This register is a read-only register. When it is read, 10H is returned. This indicates to the system that
this is an 8-bit implementation.
The bit definitions are as follows:
Bit 7: This bit is read-only. It is at low level during a read. This means that this chip does not support
Bit 6: Returns the value on the ISA IRQ line to determine possible conflicts.
5.3.5
5.3.6
5.3.7
5.3.8
5.3.9
hardware RLE compression.
CFIFO (Parallel Port Data FIFO) Mode = 010
ECPDFIFO (ECP Data FIFO) Mode = 011
TFIFO (Test FIFO Mode) Mode = 110
CNFGA (Configuration Register A) Mode = 111
CNFGB (Configuration Register B) Mode = 111
7
6
5
4
-64 -
3
1
2
1
1
0
1
compress
IRQx 0
IRQx 1
IRQx 2
intrValue
Publication Release Date: April 2003
W83977EF
Revision 1.1