W83977EF Winbond Electronics Corp America, W83977EF Datasheet - Page 56

• Manufacturer Part Number: W83977EF
• Description: Description = W83877TF Plus Kbc, GP I/O, Wake-Up, Power Fail Resume ;; Package = QFP 128
• Manufacturer: Winbond Electronics Corp America

Bit 6: This bit is the opposite of the RI # input. This bit is equivalent to bit 2 of HCR in loopback
Bit 5: This bit is the opposite of the DSR# input. This bit is equivalent to bit 0 of HCR in loopback
Bit 4: This bit is the opposite of the CTS# input. This bit is equivalent to bit 1 of HCR in loopback
Bit 3: TDCD. This bit indicates that the DCD# pin has changed state after HSR was read by the CPU.
Bit 2: FERI. This bit indicates that the RI # pin has changed from low to high state after HSR was
Bit 1: TDSR. This bit indicates that the DSR# pin has changed state after HSR was read by the CPU.
Bit 0: TCTS. This bit indicates that the CTS# pin has changed state after HSR was read.
This register is used to control the FIFO functions of the UART.
Bit 6, 7: These two bits are used to set the active level for the receiver FIFO interrupt. For example, if
TABLE 3-3 FIFO TRIGGER LEVEL
Bit 4, 5: Reserved
Bit 3: When this bit is programmed to logic 1, the DMA mode will change from mode 0 to mode 1 if
Bit 2: Setting this bit to a logical 1 resets the TX FIFO counter logic to initial state. This bit will clear to
3.2.5 UART FIFO Control Register (UFR) (Write only)
BIT 7
read by the CPU.
the interrupt active level is set as 4 bytes, once there are more than 4 data characters in the
receiver FIFO, the interrupt will be activated to notify the CPU to read the data from the FIFO.
UFR bit 0 = 1.
a logical 0 by itself after being set to a logical 1.
0
0
1
1
mode.
mode.
mode.
BIT 6
0
1
0
1
7
6
RX FIFO INTERRUPT ACTIVE LEVEL (BYTES)
5
4
3
2
-50 -
1
0
01
04
08
14
FIFO enable
Receiver FIFO reset
Transmitter FIFO reset
DMA mode select
Reserved
Reserved
RX interrupt active level (LSB)
RX interrupt active level (MSB)
Publication Release Date: April 2003
W83977EF
Revision 1.1