W83977EF Winbond Electronics Corp America, W83977EF Datasheet - Page 52

• Manufacturer Part Number: W83977EF
• Description: Description = W83877TF Plus Kbc, GP I/O, Wake-Up, Power Fail Resume ;; Package = QFP 128
• Manufacturer: Winbond Electronics Corp America

BDLAB = 0
BDLAB = 0
BDLAB = 0
BDLAB = 1
BDLAB = 1
+ 0
+ 0
+ 1
+ 2
+ 2
+ 3
+ 4
+ 5
+ 6
+ 7
+ 0
+ 1
*: Bit 0 is the least significant bit. The least significant bit is the first bit serially transmitted or received.
**: These bits are always 0 in 16450 Mode.
Interrupt Control
Status Register
Interrupt Status
Buffer Register
UART Control
UART Status
User Defined
Divisor Latch
Divisor Latch
(Read Only)
(Write Only)
(Read Only)
UART FIFO
(Write Only)
Transmitter
Handshake
Handshake
Receiver
Baudrate
Baudrate
Register
Register
Register
Register
Register
Register
Register
Register
Control
Control
Buffer
High
Low
RBR
UCR
HCR
USR
HSR
UDR
TBR
UFR
BHL
BLL
ICR
ISR
RBR Data
RBR Data
RX Data
TX Data
Terminal
(ERDRI)
Toggling
Interrupt
Interrupt
Pending
(DLS0)
(TCTS)
Enable
Enable
Length
Ready
Ready
Ready
Select
(RDR)
(DTR)
FIFO
Bit 0
Bit 0
"0" if
Data
Bit 0
Data
CTS
Bit 0
Bit 0
Bit 8
(ETBREI)
RX Data
Interrupt
Interrupt
Request
Toggling
TX Data
Overrun
(TDSR)
Enable
(DLS1)
Length
Status
Empty
RCVR
Select
(OER)
Bit (0)
Reset
(RTS)
FIFO
Send
Data
Error
DSR
Bit 1
Bit 1
TBR
Bit 1
Bit 1
Bit 1
Bit 9
to
-46 -
Loopback
RI Falling
Stop Bits
Parity Bit
RX Data
TX Data
(EUSRI)
Interrupt
(MSBE)
Interrupt
Multiple
(PBER)
Enable
Enable
(FERI)
Status
Bit (1)
Reset
Bit 10
XMIT
Edge
FIFO
Input
Error
Bit 2
Bit 2
Bit 2
Bit 2
USR
RI
RX Data
Toggling
TX Data
Interrupt
(EHSRI)
Interrupt
No Stop
Bit (2)**
(NSER)
(TDCD)
Enable
Enable
Enable
Status
Select
(PBE)
Mode
Parity
Bit 11
DMA
Error
DCD
HSR
Bit 3
Bit 3
Bit 3
Bit 3
IRQ
Bit
Bit
Publication Release Date: April 2003
Reserved
Loopback
Detected
RX Data
TX Data
to Send
Internal
Enable
Enable
(SBD)
Parity
(EPE)
(CTS)
Bit 12
Silent
Clear
Even
Bit 4
Bit 4
Byte
Bit 4
Bit 4
0
0
Reversed
RX Data
TX Data
Bit Fixed
Data Set
(TBRE)
Enable
PBFE)
Empty
Ready
(DSR)
Parity
Bit 13
W83977EF
Bit 5
Bit 5
TBR
Bit 5
Bit 5
0
0
0
Active Level
Revision 1.1
RX Data
Indicator
TX Data
Enabled
Interrupt
(TSRE)
Silence
Enable
FIFOs
Empty
(SSE)
(LSB)
Bit 14
Bit 6
Bit 6
TSR
Ring
Bit 6
Bit 6
(RI)
Set
RX
**
0
0
Data Carrier
Active Level
Access Bit
Indication
RX Data
Baudrate
(RFEI) **
(BDLAB)
RX FIFO
Interrupt
TX Data
Enabled
Divisor
(MSB)
Detect
(DCD)
FIFOs
Bit 15
Latch
Error
Bit 7
Bit 7
Bit 7
Bit 7
RX
**
0
0