at91sam9263 ATMEL Corporation, at91sam9263 Datasheet - Page 288

• Manufacturer Part Number: at91sam9263
• Description: At91 Arm Thumb Microcontrollers
• Manufacturer: ATMEL Corporation

Figure 24-9. Multi-Block DMA Transfer with Source and Destination Address Auto-reloaded
6249D–ATARM–20-Dec-07
Source Layer
Address of
a. If interrupts are enabled (DMAC_CTLx.INT_EN = 1) and the block complete inter-
b. If interrupts are disabled (DMAC_CTLx.INT_EN = 0) or the block complete interrupt
SAR
rupt is un-masked (DMAC_MaskBlock[x] = 1’b1, where x is the channel number)
hardware sets the block complete interrupt when the block transfer has completed.
It then stalls until the block complete interrupt is cleared by software. If the next
block is to be the last block in the DMA transfer, then the block complete ISR (inter-
rupt service routine) should clear the reload bits in the DMAC_CFGx.RELOAD_SR
and DMAC_CFGx.RELOAD_DS registers. This put the DMAC into Row 1 as
shown in
transfer, then the reload bits should remain enabled to keep the DMAC in Row 4.
is masked (DMAC_MaskBlock[x] = 1’b0, where x is the channel number), then
hardware does not stall until it detects a write to the block complete interrupt clear
register but starts the next block transfer immediately. In this case software must
clear the reload bits in the DMAC_CFGx.RELOAD_SR and
DMAC_CFGx.RELOAD_DS registers to put the DMAC into ROW 1 of
on page 278
is similar to that shown in
in
Figure 24-10 on page
Source Blocks
Table 24-2 on page
before the last block of the DMA transfer has completed. The transfer
Block2
Block0
Block1
BlockN
289.
Figure 24-9 on page
Destination Blocks
278. If the next block is not the last block in the DMA
AT91SAM9263 Preliminary
Destination Layer
288. The DMA transfer flow is shown
DAR
Address of
Table 24-2
288