zl30119 Zarlink Semiconductor, zl30119 Datasheet - Page 11

• Manufacturer Part Number: zl30119
• Description: Low Jitter Line Card Synchronizer
• Manufacturer: Zarlink Semiconductor

1.0
The ZL30119 SONET/SDH Line Card Synchronizer is a highly integrated device that provides timing and
synchronization for network interface cards. It incorporates two independent DPLLs, each capable of locking to one
of eight input references and provides a wide variety of synchronized output clocks and frame pulses.
1.1
The ZL30119 provides two independently controlled Digital Phase-Locked Loops (DPLL1, DPLL2) for clock and/or
frame pulse synchronization. Table 1 lists the feature summary for both DPLLs.
Modes of Operation
Loop Bandwidth
Phase Slope Limiting
Pull-in Range
Reference Inputs
Sync Inputs
Input Ref Frequencies
Supported Sync Input
Frequencies
Input Reference
Selection/Switching
Hitless Ref Switching
Output Clocks
Output Frame Pulses
Supported Output Clock
Frequencies
Supported Output
Frame Pulse
Frequencies
External Pins Status
Indicators
1. In the wideband mode, the loop bandwidth depends on the frequency of the reference input. For reference frequencies equal to or
greater than 64 kHz, the loop bandwidth = 890 Hz. For reference frequencies equal to or greater than 8 kHz and less than 64 kHz, the
loop bandwidth = 56 Hz. For reference frequencies equal to 2 kHz, the loop bandwidth is equal to 14 Hz.
DPLL Features
Functional Description
Feature
Free-run, Normal (locked), Holdover
User selectable: 14 Hz, 28 Hz, or
wideband
User selectable: 885 ns/s, 7.5 2s/s,
61 2s/s, or unlimited
Fixed: 130 ppm
Ref0 to Ref7
Sync0, Sync1, Sync2
2 kHz, N * 8 kHz up to 77.76 MHz
166.67 Hz, 400 Hz, 1 kHz, 2 kHz,
8 kHz, 64 kHz.
Automatic (based on programmable
priority and revertiveness), or manual
Can be enabled or disabled
diff0_p/n, diff1_p/n, sdh_clk0, sdh_clk1,
p0_clk0, p0_clk1, p1_clk0, p1_clk1,
fb_clk.
sdh_fp0, sdh_fp1, p0_fp0, p0_fp1
synchronized to active sync reference.
As listed in Table 4
As listed in Table 4
Lock, Holdover
Table 1 - DPLL1 and DPLL2 Features
1
(890 Hz / 56 Hz / 14 Hz)
DPLL1
Zarlink Semiconductor Inc.
ZL30119
11
Free-run, Normal (locked), Holdover.
Fixed: 14 Hz
User selectable: 61 2s/s, or unlimited
Fixed: 130 ppm
Ref0 to Ref7
Sync inputs are not supported.
2 kHz, N * 8 kHz up to 77.76 MHz
Sync inputs are not supported.
Automatic (based on programmable
priority and revertiveness), or manual
Can be enabled or disabled
p0_clk0, p0_clk1, p1_clk0, p1_clk1.
p0_fp0, p0_fp1 not aligned to sync
reference.
As listed in Table 4 for p0_clk0, p0_clk1,
p1_clk0, p1_clk1
As listed in Table 4 for p0_fp0, p0_fp not
aligned to sync reference.
None
DPLL2
Data Sheet