zl30119 Zarlink Semiconductor, zl30119 Datasheet - Page 13

• Manufacturer Part Number: zl30119
• Description: Low Jitter Line Card Synchronizer
• Manufacturer: Zarlink Semiconductor

1.3
There are eight reference clock inputs (ref0 to ref7) available to both DPLL1 and DPLL2. The selected reference
input is used to synchronize the output clocks. Each of the DPLLs have independent reference selectors which can
be controlled using a built-in state machine or set in a manual mode.
In addition to the reference inputs, DPLL1 has three optional frame pulse synchronization inputs (sync0 to sync2)
used to align the output frame pulses. The sync
or 2. Note that the sync input cannot be used to synchronize the DPLL, it only determines the alignment of the
frame pulse outputs. An example of output frame pulse alignment is shown in Figure 4.
When a frame pulse
signal is present at the
sync input, the DPLL
will align the output
frame pulses to the
output clock edge that is
aligned to the input
frame pulse.
Without a frame pulse
signal at the sync input,
the output frame pulses
will align to any arbitrary
cycle of its associated
output clock.
Ref and Sync Inputs
n = 0, 1, 2
x = 0, 1
n = 0, 1, 2
x = 0, 1
sync2:0
ref7:0
sdh/p0/p1_clk
Figure 4 - Output Frame Pulse Alignment
sdh/p0/p1_clk
Figure 3 - Reference and Sync Inputs
sdh/p0_fp
sdh/p0_fp
sync
Zarlink Semiconductor Inc.
sync
n
ref
ref
input is selected with its corresponding ref
ZL30119
n
n
x
x
n
x
x
n
- no frame pulse signal present
13
DPLL2
DPLL1
n
input, where n = 0, 1,
Data Sheet