zl30119 Zarlink Semiconductor, zl30119 Datasheet - Page 8

• Manufacturer Part Number: zl30119
• Description: Low Jitter Line Card Synchronizer
• Manufacturer: Zarlink Semiconductor

Status
Serial Interface
APLL Loop Filter
JTAG and Test
Pin #
H1
G1
G2
C6
H4
E2
F1
E3
A6
B6
K2
K3
J1
J4
J3
dpll1_holdover
dpll1_lock
sdh_filter
filter_ref0
filter_ref1
Name
trst_b
int_b
cs_b
tms
sck
tdo
tck
so
tdi
si
Type
I/O
O
O
O
I
O
O
I
I
I
A
A
A
I
I
I
u
u
u
u
Lock Indicator (LVCMOS). This is the lock indicator pin for DPLL1. This output
goes high when DPLL1’s output is frequency and phase locked to the input
reference.
Holdover Indicator (LVCMOS). This pin goes high when DPLL1 enters the
holdover mode.
Clock for Serial Interface (LVCMOS). Serial interface clock.
Serial Interface Input (LVCMOS). Serial interface data input pin.
Serial Interface Output (LVCMOS). Serial interface data output pin.
Chip Select for Serial Interface (LVCMOS). Serial interface chip select. This
pin is internally pull up to Vdd.
Interrupt Pin (LVCMOS). Indicates a change of device status prompting the
processor to read the enabled interrupt service registers (ISR). This pin is an
open drain, active low and requires an external pull up to VDD.
External Analog PLL Loop Filter terminal.
Analog PLL External Loop Filter Reference.
Analog PLL External Loop Filter Reference.
Test Serial Data Out (Output). JTAG serial data is output on this pin on the
falling edge of tck. This pin is held in high impedance state when JTAG scan is
not enabled.
Test Serial Data In (Input). JTAG serial test instructions and data are shifted in
on this pin. This pin is internally pull up to Vdd. If this pin is not used then it
should be left unconnected.
Test Reset (LVCMOS). Asynchronously initializes the JTAG TAP controller by
putting it in the Test-Logic-Reset state. This pin should be pulsed low on power-
up to ensure that the device is in the normal functional state. This pin is internally
pulled up to Vdd. If this pin is not used then it should be connected to GND.
Test Clock (LVCMOS): Provides the clock to the JTAG test logic. If this pin is not
used then it should be pulled down to GND.
Test Mode Select (LVCMOS). JTAG signal that controls the state transitions of
the TAP controller. This pin is internally pulled up to V
then it should be left unconnected.
Zarlink Semiconductor Inc.
ZL30119
8
Description
DD
. If this pin is not used
Data Sheet