zl30119 Zarlink Semiconductor, zl30119 Datasheet - Page 23

• Manufacturer Part Number: zl30119
• Description: Low Jitter Line Card Synchronizer
• Manufacturer: Zarlink Semiconductor

(Hex)
Addr
5E
6A
6B
6C
6D
5F
60
61
62
63
64
65
66
67
68
69
sdh_fp1_offset_1
sdh_fp1_offset_2
diff_ctrl
diff_sel
fb_control
fb_offset_fine
reserved
ref_freq_mode_0
ref_freq_mode_1
custA_mult_0
custA_mult_1
custA_scm_low
custA_scm_high
custA_cfm_low_0
custA_cfm_low_1
custA_cfm_hi_0
Register
Name
Table 5 - Register Map (continued)
Custom Input Frequencies
Reset
Value
(Hex)
Differential Output Configuration
External Feedback Configuration
A3
00
00
53
81
F5
00
00
00
00
00
00
00
00
00
Zarlink Semiconductor Inc.
ZL30119
Bits [15:8] of the programmable frame pulse
Bits [21:16] of the programmable frame pulse
Control register to select the diff0 and diff1
Control register to set whether to use auto
Control register to set whether to use auto
Control register for the [7:0] bits of the custom
Control register for the [13:8] bits of the custom
Control register for the custom configuration A:
Control register for the custom configuration
Control register for the custom configuration
Control register for the custom configuration
Control register for the custom configuration
phase offset in multiples of 1/311.04 MHz
phase offset in multiples of 8 kHz cycles
Control register to enable diff0, diff1 and
diffout1_high
frequencies
Control register to enable fb_clk and the FB
PLL, int/ext feedback select
Control register for the output/output phase
alignment fine tuning
detect, CustomA or CustomB for ref0 to ref3
detect, CustomA or CustomB for ref4 to ref7
configuration A. This is the N integer for the
N*8kHz reference monitoring.
configuration A. This is the N integer for the
N*8kHz reference monitoring.
single cycle SCM low limiter
A: single cycle SCM high limiter
A: The [7:0] bits of the single cycle CFM low
limit
A: The [15:0] bits of the single cycle CFM low
limit
A: The [7:0] bits of the single cycle CFM high
limit
23
Description
Data Sheet
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W