zl30119 Zarlink Semiconductor, zl30119 Datasheet - Page 20

• Manufacturer Part Number: zl30119
• Description: Low Jitter Line Card Synchronizer
• Manufacturer: Zarlink Semiconductor

(Hex)
Addr
2A
2B
2C
2D
2E
23
24
25
26
27
28
29
2F
30
31
32
33
34
35
dpll1_ref_rev_ctrl
dpll1_ref_pri_ctrl_0
dpll1_ref_pri_ctrl_1
dpll1_ref_pri_ctrl_2
dpll1_ref_pri_ctrl_3
dpll1_lock_holdover_status
reserved
dpll2_ctrl_0
dpll2_ctrl_1
dpll2_modesel
dpll2_refsel
dpll2_ref_fail_mask
dpll2_wait_to_restore
dpll2_ref_rev_ctrl
dpll2_ref_pri_ctrl_0
dpll2_ref_pri_ctrl_1
dpll2_ref_pri_ctrl_2
dpll2_ref_pri_ctrl_3
dpll2_lock_holdover_status
Register
Name
Table 5 - Register Map (continued)
Reset
Value
(Hex)
3C
00
10
32
54
76
04
03
00
04
02
00
00
00
10
32
54
76
04
Zarlink Semiconductor Inc.
P0 Configuration Registers
ZL30119
DPLL2 Control
Control register for the ref4 and re5 priority
Control register for the ref4 and re5 priority
Control register for the ref0 to ref7 enable
revertive signals
Control register for the ref0 and ref1 priority
values
Control register for the ref2 and ref3 priority
values
values
Control register for the ref6 and ref7 priority
values
DPLL1 lock and holdover status register
Leave as default
Control register to program the DPLL2: hitless
switching, the phase slope limit and DPLL
enable
Control register to program the DPLL2:
filter_out_en, freq_offset_en, revert enable
Control register to select the mode of operation
of the DPLL2
DPLL2 reference selection or reference
selection status
Control register to mask each failure indicator
(SCM, CFM, PFM and GST) used for automatic
reference switching and automatic holdover
Control register to indicate the time to restore a
previous failed reference for the DPLL2 path
Control register for the ref0 to ref7 enable
revertive signals
Control register for the ref0 and ref1 priority
values
Control register for the ref2 and ref3 priority
values
values
Control register for the ref6 and ref7 priority
values
DPLL2 lock and holdover status register
20
Description
Data Sheet
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R