zl30119 Zarlink Semiconductor, zl30119 Datasheet - Page 22

• Manufacturer Part Number: zl30119
• Description: Low Jitter Line Card Synchronizer
• Manufacturer: Zarlink Semiconductor

(Hex)
Addr
4A
4B
4C
4D
4E
5A
5B
5C
5D
4F
50
51
52
53
54
55
56
57
58
59
p1_freq_0
p1_freq_1
p1_clk0_offset90
p1_clk1_div
p1_clk1_offset90
p1_offset_fine
sdh_enable
sdh_run
sdh_clk_div
sdh_clk0_offset90
sdh_clk1_offset90
sdh_offset_fine
sdh_fp0_freq
sdh_fp0_type
sdh_fp0_offset_0
sdh_fp0_offset_1
sdh_fp0_offset_2
sdh_fp1_freq
sdh_fp1_type
sdh_fp1_offset_0
Register
Name
Table 5 - Register Map (continued)
Reset
Value
(Hex)
C1
00
00
3F
00
00
8F
0F
42
00
00
00
05
23
00
00
00
03
03
00
SDH Configuration Registers
Zarlink Semiconductor Inc.
ZL30119
Control register for the [7:0] bits of the N of
Control register for the p1_clk0 phase position
Control register for the p1_clk1 frequency
Control register for the p1_clk1 phase position
Control register to enable sdh_clk0, sdh_clk1,
Control register for the sdh_clk0 phase position
Control register for the sdh_clk1 phase position
Control register for the output/output phase
Bits [7:0] of the programmable frame pulse
Bits [15:8] of the programmable frame pulse
Bits [21:16] of the programmable frame pulse
Bits [7:0] of the programmable frame pulse
N*8k clk0
Control register for the [13:8] bits of the N of
N*8k clk0
coarse tuning
selection
coarse tuning
Control register for the output/output phase
alignrment fine tuning
sdh_fp0, sdh_fp1 and the SDH PLL
Control register to generate sdh_clk0,
sdh_clk1, sdh_fp0 and sdh_fp1
Control register for the sdh_clk0 and sdh_clk1
frequency selection
coarse tuning
coarse tuning
alignrment fine tuning for sdh path
Control register to select the sdh_fp0 frame
pulse frequency
Control register to select fp0 type
phase offset in multiples of 1/311.04 MHz
phase offset in multiples of 1/311.04 MHz
phase offset in multiples of 8 kHz cycles
Control register to select sdh_fp1 frame pulse
frequency
Control register to select fp1 type
phase offset in multiples of 1/311.04 MHz
22
Description
Data Sheet
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W