zl30119 Zarlink Semiconductor, zl30119 Datasheet - Page 14

• Manufacturer Part Number: zl30119
• Description: Low Jitter Line Card Synchronizer
• Manufacturer: Zarlink Semiconductor

Each of the ref inputs accept a single-ended LVCMOS clock with a frequency ranging from 2 kHz to 77.76 MHz.
Built-in frequency detection circuitry automatically determines the frequency of the reference if its frequency is
within the set of pre-defined frequencies as shown in Table 2. Custom frequencies definable in multiples of 8 kHz
are also available.
Each of the sync inputs accept a single-ended LVCMOS frame pulse. Since alignment is determined from the rising
edge of the frame pulse, there is no duty cycle restriction on this input, but there is a minimum pulse width
requirement of 5 ns. Frequency detection for the sync inputs is automatic for the supported frame pulse frequencies
shown in Table 3.
1.4
All input references (ref0 to ref7) are monitored for frequency accuracy and phase regularity. New references are
qualified before they can be selected as a synchronization source, and qualified references are continuously
monitored to ensure that they are suitable for synchronization. The process of qualifying a reference depends on
four levels of monitoring.
Single Cycle Monitor (SCM)
The SCM block measures the period of each reference clock cycle to detect phase irregularities or a missing clock
edge. In general, if the measured period deviates by more than 50% from the nominal period, then an SCM failure
(scm_fail) is declared.
Ref and Sync Monitoring
Table 2 - Set of Pre-Defined Auto-Detect Clock Frequencies
Table 3 - Set of Pre-Defined Auto-Detect Sync Frequencies
Zarlink Semiconductor Inc.
(48x 125 2s frames)
ZL30119
16.384 MHz
1.544 MHz
2.048 MHz
8.192 MHz
19.44 MHz
38.88 MHz
77.76 MHz
166.67 Hz
Custom A
Custom B
6.48 MHz
400 Hz
64 kHz
64 kHz
2 kHz
8 kHz
1 kHz
2 kHz
8 kHz
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Data Sheet