zl30119 Zarlink Semiconductor, zl30119 Datasheet - Page 16

• Manufacturer Part Number: zl30119
• Description: Low Jitter Line Card Synchronizer
• Manufacturer: Zarlink Semiconductor

The feedback clock (fb_clk) of DPLL1 is available as an output clock. Its output frequency is always equal to
DPLL1’s selected input frequency.
The output clocks and frame pulses derived from the SONET/SDH APLL are always synchronous with DPLL1, and
the clocks and frame pulses generated from the programmable synthesizers can be synchronized to either DPLL1
or DPLL2. This allows the ZL30119 to have two independent timing paths.
The supported frequencies for the output clocks and frame pulses are shown in Table 4.
155.52 MHz
311.04 MHz
622.08 MHz
19.44 MHz
38.88 MHz
51.84 MHz
77.76 MHz
(LVPECL)
diff0_p/n,
6.48 MHz
diff1_p/n
DPLL2
DPLL1
(LVCMOS)
12.96 MHz
19.44 MHz
25.92 MHz
38.88 MHz
51.84 MHz
77.76 MHz
sdh_clk0,
sdh_clk1
6.48 MHz
9.72 MHz
Table 4 - Output Clock and Frame Pulse Frequencies
Figure 6 - Output Clock Configuration
p0_clk0, p1_clk0
N * 8 kHz (up to
Zarlink Semiconductor Inc.
77.76 MHz)
(LVCMOS)
ZL30119
2 kHz
16
SONET/SDH
Synthesizer
Synthesizer
Synthesizer
Feedback
APLL
P0
P1
p
p0_clk1, p1_clk1
x
_clk1 =
(LVCMOS)
p
x
p0_clk0
p0_fp0
p0_clk1
p0_fp1
p1_clk0
p1_clk1
sdh_clk0
sdh_fp0
sdh_clk1
sdh_fp1
_clk0
diff0
diff1
fb_clk
2
M
(48x 125 2s frames)
sdh_fp0, shd_fp1,
p0_fp0, p0_fp1
(LVCMOS)
166.67 Hz
400 Hz
32 kHz
64 kHz
1 kHz
2 kHz
4 kHz
8 kHz
Data Sheet